The first constraint is specifying a particular clock and naming it so the clock can easily be referenced later. I thought the set_input_delay property tells Vivado to latch the data at a specified delay, due to there being an input delay between the rising edge of the clock and when the data actually changes.
However, what confuses me is I believe that the MDIO data changes based on the MDC output clock (max frequency of 2.5 MHz). So why is the input delay defined by the 125 MHz, CLKOUT1?
Furthermore, Vivado is telling me the project didn't reach proper timing for the MDIO inout port to IP core datapath. This error goes away when I comment out the set_input_delay constraint - and my code appears to run perfectly fine. So I'm questionning if this constraint is even needed in the first place?
I added the set_input_delay constraint to my project because the IP Core Product Guide said to base my project constraints off of the example project's. But the guide didn't specify the particulars of any of the example design constraints.