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Visitor
Visitor
1,964 Views
Registered: ‎08-21-2017

UCF: How to specify an async Pad to Pad delay

Dear experts,

I currently deal with a quite simple issue.

I just want to define a Timing constraint for the Inputs and the Output of a multiplexer. The multiplexer is controlled by a Register that is inside the FPGA. 

Inputs are the FPGA Pads "P_A_in"  and  "P_B_in". Output is the pad "P_out"

 

I enter the following in my UCF file:

NET "P_A_IN" TNM_NET  = TNM_P_A_IN;
NET "P_OUT" TNM_NET = TNM_P_OUT;
TIMESPEC "TS_DELAY" = from TNM_P_IN to TNM_P_OUT 6 ns DATAPATHONLY;

 

But when compiling the design I finnally get the following Timing Report:

TS_DELAY = MAXDELAY FROM TIMEGRP "TNM_P_IN" TO TIMEGRP "TNM_P_OUT" 6ns;

0 items analyzed, 0 Timing Errors detected.

 

Actually I don't know why my simple combinatorial path from Input Pad to Output Pad is not analyzed.

What did I do wrong?

How can I achieve this constraint?

Please help. Any comments are welcome. It's quite urgent ;-(

 

 

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Guide
Guide
1,957 Views
Registered: ‎01-23-2009

Please don't post the same question more than once (although this looks like it was probably done by accident).

 

See the replies to the other post.

 

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