cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jeevanreddymandali
Adventurer
Adventurer
14,972 Views
Registered: ‎11-03-2013

UCF warning 204 while implementing my design

Jump to solution

Hey guys, wrote my first UCF and got this warning because of which my core could not be detected in the chiopscope pro tool. In my project I am using like two independent tiles of the same GTX. I selected GTXD5(X0Y5) as my tile.

WARNING:ConstraintSystem:204 - A target design object for the Locate constraint
'<INST aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i
LOC=GTX_DUAL_X0Y5;> [aurora_8b10b_v6_1_example_design.ucf(124)]' could not be
found and so the Locate constraint will be removed.

WARNING:NgdBuild:1012 - The constraint <INST
aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i LOC=GTX_DUAL_X0Y5;>
[aurora_8b10b_v6_1_example_design.ucf(124)] is overridden on the design
object aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i by the
constraint <INST aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i
LOC=GTX_DUAL_X0Y4;> [aurora_8b10b_v6_1_example_design.ucf(125)].

 

 

jeevanreddymandali
Tags (2)
0 Kudos
Reply
1 Solution

Accepted Solutions
vemulad
Xilinx Employee
Xilinx Employee
23,232 Views
Registered: ‎09-20-2012

Open technology schematic and search for the instance gtx_tile_i. Take the complete hierarchical name of this instance from here and use it in UCF.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos
Reply
8 Replies
kotir
Scholar
Scholar
14,965 Views
Registered: ‎02-03-2010

Hi ,

 

The ConstraintSystem:204 warning seems to be due the design hierarchy is not proper in the ucf.

Check you can specify the hierachy in the  frop toplevel file till the gt instance.

 

The other is due to the location constraint is specified multiple times.

 

Regards,

KR

--------------------------------------------------​--------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Reply
vemulad
Xilinx Employee
Xilinx Employee
23,233 Views
Registered: ‎09-20-2012

Open technology schematic and search for the instance gtx_tile_i. Take the complete hierarchical name of this instance from here and use it in UCF.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos
Reply
athandr
Xilinx Employee
Xilinx Employee
14,953 Views
Registered: ‎07-31-2012

Hi,

 

1) Firstly looks like you have 2 constraints for the same instantiation.

 

GTX_DUAL_X0Y5 and GTX_DUAL_X0Y5

 

Make sure you have only 1 LOC constraint for the particular instantiation.

 

2) Make sure the syntax is  correct as below.

       

       INST “instance_name ” LOC=location;

 

3) Make sure the file name which you are giving in the XDC is correct and the directory path does not have any special characters and has read permissions.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Reply
jeevanreddymandali
Adventurer
Adventurer
14,932 Views
Registered: ‎11-03-2013

Guys, I am using a Virtex-5, xc5vfx100t-ff1136-1 device. xilinx clearly tells its customers to use all the tiles to ensure correct clock working. But in my case, as per the order of my boss, I had to use X0Y5 and in that too I should use both tiles as independent without channel bonding. So, after some searching I came to know that I can do this by selecting only one tile either X0Y5_0 or X0Y5_1 of X0Y5 and duplicate some signals and I can make that work like both tiles used but independently. So, as these FPGAs in case of Xilinx have shared clocks, in my board I get direct clock to X0Y3, but I cannot use that.

Then I came to know that if I use tiles like this, without proper order, there might be clocking dependancy errors and i should instantiate the tiles that are in between my tile and from X0Y5. Which means I have to instantiate from X0Y0 to X0Y4 in my UCF, even if I dont use them.

Please correct me if I am wrong in any aspect. I am in my starting days with FPGAs. And thanks for making time already for answering my question previously. I am attaching my UCF.

Here I instantiated X0Y4 because previously i got an error message X0Y4 should be instantiated inorder to use X0Y5. But I am planning to instantiate all from X0Y0 to X0Y5 tommorrow.

################################ CLOCK CONSTRAINTS ##############################

# User Clock Constraint: Value is selected based on the line rate (3.125 Gbps) and lane width (2-Byte)

NET "user_clk_i" TNM_NET = USER_CLK;

TIMESPEC TS_USER_CLK_I = PERIOD "USER_CLK" 6.4 ns HIGH 50%;

 

# Sync Clock Constraint: Value is selected based on the line rate (3.125 Gbps) and lane width (2-Byte)

NET sync_clk_i PERIOD = 6.4 ns HIGH 50%;

 

# 156.25MHz GTX Reference clock constraint

NET GTXD5_left_i PERIOD = 6.4 ns HIGH 50%;

 

# 50MHz board Clock Constraint 

NET "reset_logic_i/init_clk_i" TNM_NET = INIT_CLK;

TIMESPEC TS_INIT_CLK = PERIOD "INIT_CLK" 20 ns HIGH 50%;

 

###### No cross clock domain analysis. Domains are not related ##############

TIMESPEC "TS_TIG1" = FROM "INIT_CLK" TO "USER_CLK" TIG;

 

################################ Init Clock Constraint ##########################

NET INIT_CLK        LOC=AH18;   #50 Mhz Oscillator

 

################## GTX CLOCK Locations of the pins on ML523 ###############################

NET GTXD5_P  LOC=Y4;

NET GTXD5_N  LOC=Y3;

 

################################ Resets Buttons #################################

#NET RESET           LOC=AG7;   #BUTTON

 

INST aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i LOC=GTX_DUAL_X0Y5;

INST aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i LOC=GTX_DUAL_X0Y4;

jeevanreddymandali
Tags (1)
0 Kudos
Reply
jeevanreddymandali
Adventurer
Adventurer
14,931 Views
Registered: ‎11-03-2013

Hello Deepika, I did what you said, and I found this: INST aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i LOC=GTX_DUAL_X0Y5; The one I already used in my UCF.

Regards,

jeevanreddymandali
0 Kudos
Reply
athandr
Xilinx Employee
Xilinx Employee
14,897 Views
Registered: ‎07-31-2012

Hi Jeevanreddy,

 

INST aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i LOC=GTX_DUAL_X0Y5;

INST aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i LOC=GTX_DUAL_X0Y4;

 

The above looks wrong as you have two different LOC constraints to the same gt instantiatino. Comment one of them and try if you are able to implement. now. Note that for each GT in the tile you have a different instantiation and for each instantiation you have a different location constraint.

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
0 Kudos
Reply
jeevanreddymandali
Adventurer
Adventurer
14,891 Views
Registered: ‎11-03-2013
Hello, thanks for your time! I am using X0Y5, so I guess I should not comment its instantiation, if i am correct. And if i comment that X0Y4 thing, i am getting an error during the implementation, Tile X0Y4 should be instantiated if you want to use X0Y5. Thats the reason why I actually inserted the X0Y4's constraint in the UCF. So, what to do now?
jeevanreddymandali
0 Kudos
Reply
jeevanreddymandali
Adventurer
Adventurer
14,846 Views
Registered: ‎11-03-2013
Hey thanks deepika, you were correct I missed the complete hierarchial name. pff. Thanks!
jeevanreddymandali
0 Kudos
Reply