Guys, I am using a Virtex-5, xc5vfx100t-ff1136-1 device. xilinx clearly tells its customers to use all the tiles to ensure correct clock working. But in my case, as per the order of my boss, I had to use X0Y5 and in that too I should use both tiles as independent without channel bonding. So, after some searching I came to know that I can do this by selecting only one tile either X0Y5_0 or X0Y5_1 of X0Y5 and duplicate some signals and I can make that work like both tiles used but independently. So, as these FPGAs in case of Xilinx have shared clocks, in my board I get direct clock to X0Y3, but I cannot use that.
Then I came to know that if I use tiles like this, without proper order, there might be clocking dependancy errors and i should instantiate the tiles that are in between my tile and from X0Y5. Which means I have to instantiate from X0Y0 to X0Y4 in my UCF, even if I dont use them.
Please correct me if I am wrong in any aspect. I am in my starting days with FPGAs. And thanks for making time already for answering my question previously. I am attaching my UCF.
Here I instantiated X0Y4 because previously i got an error message X0Y4 should be instantiated inorder to use X0Y5. But I am planning to instantiate all from X0Y0 to X0Y5 tommorrow.
################################ CLOCK CONSTRAINTS ##############################
# User Clock Constraint: Value is selected based on the line rate (3.125 Gbps) and lane width (2-Byte)
NET "user_clk_i" TNM_NET = USER_CLK;
TIMESPEC TS_USER_CLK_I = PERIOD "USER_CLK" 6.4 ns HIGH 50%;
# Sync Clock Constraint: Value is selected based on the line rate (3.125 Gbps) and lane width (2-Byte)
NET sync_clk_i PERIOD = 6.4 ns HIGH 50%;
# 156.25MHz GTX Reference clock constraint
NET GTXD5_left_i PERIOD = 6.4 ns HIGH 50%;
# 50MHz board Clock Constraint
NET "reset_logic_i/init_clk_i" TNM_NET = INIT_CLK;
TIMESPEC TS_INIT_CLK = PERIOD "INIT_CLK" 20 ns HIGH 50%;
###### No cross clock domain analysis. Domains are not related ##############
TIMESPEC "TS_TIG1" = FROM "INIT_CLK" TO "USER_CLK" TIG;
################################ Init Clock Constraint ##########################
NET INIT_CLK LOC=AH18; #50 Mhz Oscillator
################## GTX CLOCK Locations of the pins on ML523 ###############################
NET GTXD5_P LOC=Y4;
NET GTXD5_N LOC=Y3;
################################ Resets Buttons #################################
#NET RESET LOC=AG7; #BUTTON
INST aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i LOC=GTX_DUAL_X0Y5;
INST aurora_module_i/gtx_wrapper_i/GTX_TILE_INST/gtx_tile_i LOC=GTX_DUAL_X0Y4;
jeevanreddymandali
