01-06-2020 03:18 AM
My design have enormous hold violations after placement. The skew is more than 3ns. I followed the UG1292 using report_failfast command to analyis my design. It shows that there are LUTs on the clock path. How can I fix this problem?
I used the -gated_clock_conversion option for synthesis, and I also tried phys_opt_design -hold_fix/-directive ExporeWithHoldFix after placement, but it still have large hold violations.
01-06-2020 03:47 AM
Hi @charlie_xie ,
From your question I am not sure. Did you receive error message without -gated_clock_conversion and try this to solve the issue or did you have correct functioning design and the -gated_clock_conversion introduced the error?
01-06-2020 06:32 AM
Do you need to use gated clocks in your design ?
Each device has a limited number of buffers that can be used to gate clocks, how many gated clocks do you require ?
what is your device ?
01-07-2020 02:57 AM
My device is xcvu9p-flga2104. Actually the design is an AISC design running on FPGA for function verification. Gated clocks is needed.
The large hold violation is due to the large skew over than 3ns, so I want to remove the LUT on the clock tree. I firstly used the command:
report_methodology -checks TIMING-14 -verbose
to get the detail information of these LUTs. After excuting opt_design , two LUTs were removed but there are still 17 LUTs.
Now I'am trying different synth options to see whether these LUTs can be removed or not.
If you have other way to solve the LUTs problems , please tell me. -__- ~ .
I'm still struggling solving this problem.
01-07-2020 03:05 AM
01-07-2020 04:05 AM
Do you mean that when there are not enough clock gate buffers(BUFGCE), then LUT will be used on the clock tree?
In my understanding, this device has enough buffers to support the design. Maybe I can constrain the design better or try different syn options, which I'm trying now.