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Visitor
Visitor
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Registered: ‎12-22-2019

UltraScale+ fix "LUT on clock path" in the report_failfast report

Hi, all

My design have enormous hold violations after placement. The skew is more than 3ns. I followed the UG1292 using report_failfast command to analyis my design. It shows that there are LUTs on the clock path.  How can I fix this problem? 

I used the -gated_clock_conversion option for synthesis, and I also tried phys_opt_design -hold_fix/-directive ExporeWithHoldFix after placement, but it still have large hold violations.

 

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Adventurer
Adventurer
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Registered: ‎07-16-2009

Re: UltraScale+ fix "LUT on clock path" in the report_failfast report

Hi @charlie_xie ,

From your question I am not sure. Did you receive error message without  -gated_clock_conversion and try this to solve the issue or did you have correct functioning design and the -gated_clock_conversion introduced the error?

 

Best Regards,

Jan

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: UltraScale+ fix "LUT on clock path" in the report_failfast report

Do you need to use gated clocks in your design ?

Each device has a limited number of buffers that can be used to gate clocks, how many gated clocks do you require ?

what is your device ?

 

 

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Visitor
Visitor
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Registered: ‎12-22-2019

Re: UltraScale+ fix "LUT on clock path" in the report_failfast report

Thanks for replying.
I will try it later.


Wishes
Charile
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Visitor
Visitor
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Registered: ‎12-22-2019

Re: UltraScale+ fix "LUT on clock path" in the report_failfast report

Hi, @drjohnsmith

My device is xcvu9p-flga2104. Actually the design  is an AISC design running on FPGA for function verification. Gated clocks is needed.

The large hold violation is due to the large skew over than 3ns, so I want to remove the LUT on the clock tree. I firstly used the command:

report_methodology  -checks TIMING-14  -verbose 

to get the detail information of these LUTs. After excuting opt_design , two LUTs were removed but there are still 17 LUTs.

Now I'am trying different synth options to see whether these LUTs can be removed or not.

If you have other way to solve the LUTs problems , please tell me. -__- ~ .

I'm still struggling solving this problem.

 

Wishes

Charile

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Teacher
Teacher
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Registered: ‎07-09-2009

Re: UltraScale+ fix "LUT on clock path" in the report_failfast report

You are suffering a very common problem I have been involved with a few times,
taking ASIC code and trying to run it on an FPGA,

Problem is fundamental, FPGAs and ASICs have very different clocking technologies,

Once you have used the limited gate enable clock resources in any chip, then you have two choices, and a big question.

a) run the design slower, such that LUTs can be used
b) Change the code such that fewer gated clocks are needed

big question,
split the design over multiple FPGAs to gain more clocks with gates ,

The number of clocks than can have gates in an FPGA is getting greater over the years,
Virtex Ultrascale+ has a good few,

But ASICs are always going to need more than FPGAs can provide.

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor
Visitor
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Registered: ‎12-22-2019

Re: UltraScale+ fix "LUT on clock path" in the report_failfast report

Hi,@drjohnsmith 

Do you mean that when there are not enough clock gate buffers(BUFGCE), then LUT will be used on the clock tree?

In my understanding, this device has enough buffers to support the design. Maybe I can constrain the design better or try different syn options, which I'm trying now.

 

Wishes.

Charile