12-26-2013 12:35 PM
After checking unconstrained paths report I am wondering for a source sync.input data.
I have source synchronous data and clock coming to FPGA (spartan 6 100 , PlanAhead 14,6)
I am using a ISERDES2 primitive deserializer to deserialize the data.
Phase detection is already enabled Would it make sense if I still use "offset in" constraint?
12-26-2013 06:07 PM
1. I guess you're referring to using OFFSET IN to constrain the path from input pad to ISERDES. Input pad to IDELAY is not a valid timing path. And the answer is no. When you use IDELAY in variable mode, you don't need to add OFFSET IN constraint.
2. It depands. Some unconstrained paths can be ignored but some cannot. What unconstrained path do you have?
12-27-2013 11:43 AM
12-27-2013 10:02 PM
1. From the differential clock input to the internal registers (which are driven by the outputs of PLL,differential clock is PLL input)
----AR#18392 answers this.
You can just ignore this kind of paths
2. From the differential data input to the iserdes.m and iserdes_s. (Total delay is fixed for 9 different channels and 1.674ns)
----If these are the paths from the differential data to the data input of the ISERDES and you're using IDELAY in variable mode on these paths, you can ignore them.