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Participant
4,977 Views
Registered: ‎12-29-2016

Vivado uses 4 numbers to characterize delays - FAST_MAX, FAST_MIN, SLOW_MAX, and SLOW_MIN.

I understand the difference between FAST and SLOW is caused by conditions - temperature and voltage.

I am not sure about the difference between MIN and MAX. What sort of variance they represent?

Is this the inter-part variance - that is any particular IC may work faster - all switches will have MIN delays, while another IC may work slower with all the delays been at MAX?

Or is it some sort of intra-part variance - some of the switches within an IC may have MAX delays while other switches within the same IC may have MIN delays?

Or is it some combination of both?

1 Solution

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Guide
8,065 Views
Registered: ‎01-23-2009

FAST and SLOW refer to the "Process Corner" - the combination of Process (how fast an individual part of the manufacturing line is), Voltage and Temperature (PVT).

The MIN and MAX are for "On Chip Variation".

On a device that is at the "SLOW" process corner, not every cell on the device is identically slow; there is some variation on the die. By definition, if we are at the "SLOW" process corner then at least some cells are truly as slow as they can be - these are referred to as "SLOW_MAX". However, even on a "SLOW" die, some cells will be faster. The fastest of these are referred to as "SLOW_MIN". In essence , "SLOW_MIN" means the fastest a cell can be at a PVT corner that results in at least one cell on the same die being true "SLOW_MAX".

The FAST is the same (but opposite). "FAST_MIN" is truly the fastest a cell can be at any combination of PVT. "FAST_MAX" is the slowest a cell can be on a die that has at least one cell at "FAST_MIN".

The MIN and MAX are used during timing analysis to ensure that there is adequate pessimism in the timing analysis. For a setup check at Slow Process Corner (and remember, by default, Vivado do setup and hold checks at both slow and fast process corner), the longest delay is used for the "Source Clock Delay" and "Datapath Delay" - these are timed at SLOW_MAX. However, to ensure adequate pessimism, you have to assume that the "Destination Clock Path" may have some faster cells on it; so these cells are timed at "SLOW_MIN".

This leads to some odd results for cells that are both on the "Source Clock Delay" and "Destination Clock Delay"; for example for paths that are on the same clock, the IBUF bringing the clock in, the MMCM and the BUFG will be on both of these paths. For the "Source Clock Delay" they will be timed at "SLOW_MAX" (again, for a setup check at slow process corner), but for the "Destination Clock Delay" they will be timed at "SLOW_MIN". This leads to excessive pessimism; these cells can't simultaneously be at two different process corners. For this reason, the additional pessimism introduced by this calculation is removed at the end of the static timing analysis in the line "clock pessimism", which adds some margin back for this excessive pessimism - this is "Clock Re-convergence Pessimism Removal (CRPR)".

Avrum

Tags (3)
2 Replies
Guide
8,066 Views
Registered: ‎01-23-2009

FAST and SLOW refer to the "Process Corner" - the combination of Process (how fast an individual part of the manufacturing line is), Voltage and Temperature (PVT).

The MIN and MAX are for "On Chip Variation".

On a device that is at the "SLOW" process corner, not every cell on the device is identically slow; there is some variation on the die. By definition, if we are at the "SLOW" process corner then at least some cells are truly as slow as they can be - these are referred to as "SLOW_MAX". However, even on a "SLOW" die, some cells will be faster. The fastest of these are referred to as "SLOW_MIN". In essence , "SLOW_MIN" means the fastest a cell can be at a PVT corner that results in at least one cell on the same die being true "SLOW_MAX".

The FAST is the same (but opposite). "FAST_MIN" is truly the fastest a cell can be at any combination of PVT. "FAST_MAX" is the slowest a cell can be on a die that has at least one cell at "FAST_MIN".

The MIN and MAX are used during timing analysis to ensure that there is adequate pessimism in the timing analysis. For a setup check at Slow Process Corner (and remember, by default, Vivado do setup and hold checks at both slow and fast process corner), the longest delay is used for the "Source Clock Delay" and "Datapath Delay" - these are timed at SLOW_MAX. However, to ensure adequate pessimism, you have to assume that the "Destination Clock Path" may have some faster cells on it; so these cells are timed at "SLOW_MIN".

This leads to some odd results for cells that are both on the "Source Clock Delay" and "Destination Clock Delay"; for example for paths that are on the same clock, the IBUF bringing the clock in, the MMCM and the BUFG will be on both of these paths. For the "Source Clock Delay" they will be timed at "SLOW_MAX" (again, for a setup check at slow process corner), but for the "Destination Clock Delay" they will be timed at "SLOW_MIN". This leads to excessive pessimism; these cells can't simultaneously be at two different process corners. For this reason, the additional pessimism introduced by this calculation is removed at the end of the static timing analysis in the line "clock pessimism", which adds some margin back for this excessive pessimism - this is "Clock Re-convergence Pessimism Removal (CRPR)".

Avrum

Tags (3)
Participant
4,958 Views
Registered: ‎12-29-2016

Thank you for the excellent explanation!