Understanding report timing summary

[sarit8]

I ran report timing summary and got (for example):

Slack (MET) : 0.199ns (arrival time - required time)
Source: rx_top_i/adc_if_i/adc_data_samp_reg[7]/C
(rising edge-triggered cell FDRE clocked by clk_o250_clk_wiz_0 {rise@0.000ns fall@2.000ns period=4.000ns})
Destination: rx_top_i/rx_fe_i/dc_and_pow_est_i/x_n_no_dc_reg[7]/D
(rising edge-triggered cell FDRE clocked by clk_o125_clk_wiz_0 {rise@0.000ns fall@4.000ns period=8.000ns})
Path Group: clk_o125_clk_wiz_0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk_o125_clk_wiz_0 rise@0.000ns - clk_o250_clk_wiz_0 rise@0.000ns)
Data Path Delay: 0.794ns (logic 0.164ns (20.667%) route 0.630ns (79.333%))
Logic Levels: 0
Clock Path Skew: 0.329ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.234ns
Source Clock Delay (SCD): 0.899ns
Clock Pessimism Removal (CPR): 0.006ns
Clock Uncertainty: 0.189ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.118ns
Phase Error (PE): 0.120ns
Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1

I want to know the requirement time of this path (is it 4ns or 8ns), but I can't understand it from the report. How can I know this?

[syedz]

@sarit8,

You are seeing hold area whose requirement is 0 ns. Please check page 29 in below user guide to understand timing report summary:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug906-vivado-design-analysis.pdf

--Syed

[sarit8]

I read that:

° 0 ns when all timing constraints are met for min delay analysis

But I'm not sure what does it mean?

p.s I am using multicycle_path on pth from  {rx_top_i/adc_if_i/adc_data_samp_reg[*]/C} by the following constraints:

set_multicycle_path -setup -start -from [get_pins {rx_top_i/adc_if_i/adc_data_samp_reg[*]/C}] -to $mcp_adc_data_samp 2
set_multicycle_path -hold -from [get_pins {rx_top_i/adc_if_i/adc_data_samp_reg[*]/C}] -to $mcp_adc_data_samp 1

[arpansur]

Hi @sarit8,

You are trying to analyze multi cycle paths from fast to slow clocks and the scenario is similar to page-120 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug903-vivado-using-constraints.pdf and check the hold analysis edge.

[avrumw]

To be clear, the timing report you showed us is a hold check - you can tell by the fact that the "Path type:" is "(Hold) Min at Fast Process Corner"

Under most circumstances the "Requirement" for a hold check should be 0, as is the case with your path. This is probably correct. In fact, this is precisely what the "set_multicycle_path -hold 1" command does; it restores the hold check edges to the correct edges (with 0ns requirements).

Furthermore, the tool is telling you that it recognizes that this covered by your set_multicycle_path commands - the line " Timing Exception: MultiCycle Path Setup -start 2 Hold -start 1" means it saw both of the set_multicycle_path commands.

If you want to see the setup check you can use a command like

report_timing -setup -from [get_pins {rx_top_i/adc_if_i/adc_data_samp_reg[*]/C}] -to $mcp_adc_data_samp

(assuming you first set mcp_adc_data_samp the same way as you do in the XDC file - variables are not carried from the XDC file to the user environment).

The "-setup" (or "-delay_type max") forces it to show the setup check. By default the "delay type" is set to min_max, which will result in it reporting both setup and hold checks. Without any other options the command will report only one path - the one with the smallest slack (which in this case is the hold check, which isn't uncommon particularly for a multicycle path).

This is in fact one of the nice things about Vivado, the path enumeration you use for specifying a timing exception is exactly the same as what you would use to get a customized timing report on a particular path.

Avrum