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Registered: ‎06-08-2017

Unexpected extra latency from input ADC to output DAC


I am measuring the latency from input to output on my DSP system that includes LTC2194 ADCs for inputs, a Kintex-7 FPGA for DSP, and MAX5875 DACs for outputs.

I am clocking all components at 100 MHz.

I expected 7 cycles of latency from the LTC2194, plus an additional cycle from the ISERDESE2 used to download the data from the ADC to the FPGA, plus one more cycle from the always@ block I use to output the data to the FPGA fabric.

I connect the output of the ADC module directly to the input of the DAC module, which has one cycle of latency because of an always@ block, and then expect 9 more cycles of latency in the DAC itself.

At 100 MHz this should be 190 ns of latency total.

I measured the latency of the ADC + ADC firmware by halving the clock speed on just the ADC while keeping DAC clock speed the same. Taking the difference between latency at 50 MHz and 100 MHz should give the value for ADC + ADC firmware latency at 100 MHz. I measure this to be 100 ns, close to the 90 I expected.

Doing the same procedure for the DAC, I measure the DAC + DAC firmware latency at 100 ns. This is what I expected.

However, the total latency is about 320 ns, so I've got 120 ns (or twelve 100 MHz clock cycles) unaccounted for. This is almost double the latency I expected.

Any ideas what could cause this extra latency?

Thank you for your help.


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