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Observer pkimelman
Observer
349 Views
Registered: ‎10-28-2016

Using Constraint editor and Synthesis does not like the result (after an hour of synthesis)

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I have a Zync and it is feeding 4 clocks to me. I want to use set_clock_groups so the tool stops trying to find paths between the domains. It shows "locked" constraints for the 4 clocks but use of set_clock_groups cannot find the names - I assume maybe an order issue. So, I added my own create_clock constraints which exactly match the "pins" but give new names. These also fail. I used the constraint editor and it generated the set_clock_groups and that fails. I do not see what could possibly be wrong. The error is not reported until around 2 hours later (after synth). Note that the clocks do exist as if I implement, it shows in the timing report. 

create_clock -name PCLK -period "25" [get_pins "PS8_i/PLCLK[0]"]
create_clock -name CLK_bus -period "10" [get_pins "PS8_i/PLCLK[1]"]
create_clock -name CLK_mt -period "13.333" [get_pins "PS8_i/PLCLK[2]"]
create_clock -name CLK_spare -period "5" [get_pins "PS8_i/PLCLK[3]"]
set_clock_groups -name async1 -asynchronous -group [get_clocks PCLK] -group [get_clocks CLK_bus] \
                      -group [get_clocks CLK_mt] -group [get_clocks CLK_spare]

The error is:

  • [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group PCLK'. ["Y:/Documents/proj/Quarq_104board/Quarq_104board.srcs/constrs_1/new/sys_timing1.xdc":20]
  • [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group CLK_bus'. ["Y:/Documents/proj/Quarq_104board/Quarq_104board.srcs/constrs_1/new/sys_timing1.xdc":20]
  • [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group CLK_mt'. ["Y:/Documents/proj/Quarq_104board/Quarq_104board.srcs/constrs_1/new/sys_timing1.xdc":20]
  • [Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group CLK_spare'. ["Y:/Documents/proj/Quarq_104board/Quarq_104board.srcs/constrs_1/new/sys_timing1.xdc":20]

 

Then also the ones from the constraints editor (locked file):

[Vivado 12-4739] set_clock_groups:No valid object(s) found for '-group [get_clocks clk_pl_0]'. ["Y:/Documents/proj/Quarq_104board/Quarq_104board.srcs/constrs_1/new/logic_floorplan.xdc":26]

etc for the 4 numbered ones (which are created).

What is going on and how do I get this working?

Thanks, Paul

P.S. Vivado 2018.2 on Win 64b.

 

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Observer pkimelman
Observer
245 Views
Registered: ‎10-28-2016

Re: Using Constraint editor and Synthesis does not like the result (after an hour of synthesis)

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I managed to get this working by not using the constraints editor and by using the netname for the clock and using -add since it thinks the clocks exist but will not let me find them. This is very broken, but seems to be another one of the oddities associated with Zync.

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Xilinx Employee
Xilinx Employee
333 Views
Registered: ‎05-14-2008

Re: Using Constraint editor and Synthesis does not like the result (after an hour of synthesis)

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Could be because those pins you used to define the clocks cannot be found during Synthesis.

So those clocks do not exist DURING the Synthesis process.

Do you have any warning messages about those clocks in Synthesis?

If you open the Elaborated design, what do you get if you run below commands in the tcl console?

get_pins "PS8_i/PLCLK[0]"

get_pins "PS8_i/PLCLK[1]"

get_pins "PS8_i/PLCLK[2]"

get_pins "PS8_i/PLCLK[3]"

 

If you open Synthesized design and run the set_clock_groups constraint in the tcl console, will it give you the same [Vivado 12-4739] messages?

-vivian

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Observer pkimelman
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Registered: ‎10-28-2016

Re: Using Constraint editor and Synthesis does not like the result (after an hour of synthesis)

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No warning about them from synthesis or elab. But, implementation is complaining. Under Design Initialization it says:

[Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_pins {PS8_i/PLCLK[1]}]'. ["Y:/Documents/proj/Quarq_104board/Quarq_104board.srcs/constrs_1/new/sys_timing1.xdc":14]

Once for each of the 4. This is a complaint about my copy of the locked ones - the locked one is not complained about. The synthesis and elab do not complain at all including from the TCL command line.

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Observer pkimelman
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Registered: ‎10-28-2016

Re: Using Constraint editor and Synthesis does not like the result (after an hour of synthesis)

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OK, new info. I had to exit Vivado (to reboot Windows). When I restarted it, now it does not give any warning on create_clock from synthesis itself, but both the TCL line says no such pin and if I open Synthesized design it pops up a warning that the pins do not exist.
These are generated by the constraints editor, so no sure why it is wrong. I went to the constraints editor and asked to see the source for the constraints and I show it below.
## File name : psu_constraints.xdc
##
## Details : Constraints file
## FPGA family: zynq
## FPGA: PROD-2
## Device Size: xczu7ev
## Package: ffvc1156
## Speedgrade: -2
##
##
############################################################################
############################################################################
############################################################################
# Clock constraints #
############################################################################
create_clock -name clk_pl_0 -period "25" [get_pins "PS8_i/PLCLK[0]"]
create_clock -name clk_pl_1 -period "10" [get_pins "PS8_i/PLCLK[1]"]
create_clock -name clk_pl_2 -period "13.333" [get_pins "PS8_i/PLCLK[2]"]
create_clock -name clk_pl_3 -period "5" [get_pins "PS8_i/PLCLK[3]"]



set_property DONT_TOUCH true [get_cells "PS8_i"]

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Observer pkimelman
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311 Views
Registered: ‎10-28-2016

Re: Using Constraint editor and Synthesis does not like the result (after an hour of synthesis)

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Sorry, one more thing. I really do not care what method I have to use. I wanted to use the locked create_clock names from the tool (as shown above); but since they did not work when I used get_clock I tried to reproduce the get pins. I just want a way to get it to see the clocks in my file and let me use the set_clock_groups. Thanks, paul
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Observer pkimelman
Observer
246 Views
Registered: ‎10-28-2016

Re: Using Constraint editor and Synthesis does not like the result (after an hour of synthesis)

Jump to solution

I managed to get this working by not using the constraints editor and by using the netname for the clock and using -add since it thinks the clocks exist but will not let me find them. This is very broken, but seems to be another one of the oddities associated with Zync.

0 Kudos