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Visitor
Visitor
1,174 Views
Registered: ‎02-20-2017

Using MMCM I am getting a setup requirement of 0ns between paths from the output clock to the input clock

I am using the clocking wizard (5.4) to generate an MMCM where the input clock is 100mhz and the output is 10mhz and I am expecting these clocks to be phase aligned and delay matched.  See attached clocking wizard settings.  I am expecting the setup requirement to be about 10ns (- mistmatches) for paths between these 2 clocks but instead I see a requirement of 0ps - which is understandably impossible to meet.

 

The clock instance is below:

 


clk_wiz_0
i_clk_div(
// Clock out ports
.clk_out1(), // 25 mhz clock
.clk_out2(CAM_CLOCK), // 10mhz clock
.clk_out3(), // 5.078mhz clock
// Status and control signals
.locked(clk_div_locked),
// Clock in ports
.clk_in1( okClk )
);

 

And the path is between a flop on the 10mhz domain - where CLOCK below is connected to the clock being generated from the MMCM

 

always @( posedge CLOCK or negedge RESET_B )
if ( !RESET_B ) bank_input_reg[ bnk_num ] <= #0.1 'd0;
else if ( clk_en ) begin
if ( req_valid && ( req_bank == bnk_num ))
bank_input_reg[ bnk_num ] <= #0.1 { req_err_num, req_valid, req_ecnt, req_type, req_bank, req_tag, req_row, req_col, write_data };
else bank_input_reg[ bnk_num ]<= #0.1 'd0;
end

to the 100mhz domain

 

 always @(posedge okClk) begin

 

Below is the timing violation that Vivado is seeing:

 

I would like to understand why the tool believes there is no setup time and what I can do to resolve this issue?  Do I need to set any explicit timing relationships? My understanding is that the tool should create all timing constraints between these 2 clocks.

 

Thanks,

 

Steve

 

 

clocking options.PNG
mmcm_settings.PNG
no_setup_time.PNG
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5 Replies
Highlighted
Scholar
Scholar
1,170 Views
Registered: ‎06-20-2017

Re: Using MMCM I am getting a setup requirement of 0ns between paths from the output clock to the input clock

Select one of the paths, right click and generate a schematic, double click on the source and destination registers' clock pins, trace back to the MMCM, and then take a screen shot.

Mike
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Highlighted
Guide
Guide
1,143 Views
Registered: ‎01-23-2009

Re: Using MMCM I am getting a setup requirement of 0ns between paths from the output clock to the input clock

It appears you are crossing domains between the input of the MMCM and the output of the MMCM. This is not recommended.

 

If you need to have both the 100MHz clock and the 10MHz clock, then use two different outputs of the MMCM; one which is a x1 version of the input (i.e. 100MHz) and one which is your /10 output (i.e. 10MHz). Assuming both go through the same kind of clock buffer then you will have no problems with timing between the two domains (which will be timed at 10ns minus the skew and phase error between the domains).

 

Avrum

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Visitor
Visitor
1,082 Views
Registered: ‎02-20-2017

Re: Using MMCM I am getting a setup requirement of 0ns between paths from the output clock to the input clock

OK thanks - but I need to be phase aligned to the input clock as all the signals are synchronous to this already and I dont want to re-synchronoize them onto this new x1 clock - is there any other options?

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Highlighted
Guide
Guide
1,072 Views
Registered: ‎01-23-2009

Re: Using MMCM I am getting a setup requirement of 0ns between paths from the output clock to the input clock

One of the main functions of the MMCM is to deskew the clock (or, in other words, compensate for the insertion latency of the global clock domain).

 

So if you compare a clock coming directly from a clock capable pin and going to a BUFG against a clock coming from the clock capable pin, going through the MMCM (with a x1 multiplier) and going to a BUFG, the output of the MMCM will, in fact, be more in phase with the clock at the pin than the one that doesn't go through the MMCM.

 

So, there are very few reasons where you would want to use the clock "before" the MMCM - it is not as good for capturing input interfaces (or generating output interfaces), and you can generate as many phase related clocks as you need.

 

So - are you sure "all the signals" should be synchronous to the input clock (rather than the MMCM output clock)?

 

Avrum

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Highlighted
Visitor
Visitor
991 Views
Registered: ‎02-20-2017

Re: Using MMCM I am getting a setup requirement of 0ns between paths from the output clock to the input clock

Yes - all input signals are synchronous with the incoming 100MHZ clock.  If I recreate another 100mhz output clock from the mmcm then I believe I would need to resynchronize the incoming signals.  The clock is being created internally with a piece of IP I am using which I believe has its own MMCM which I cannot access

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