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shaikon
Voyager
Voyager
473 Views
Registered: ‎04-12-2012

Using a virtual clock in an SDR interface

Hello,

From this post:

https://forums.xilinx.com/t5/Timing-Analysis/what-is-a-virtual-clock-in-timing-constraints-and-why-do-we-need/td-p/813079

I understand that virtual clocks are used in order to correctly use exception when constraining Double Data rate interfaces - there're practically a must in that situation.

However I've also seen them used for constraining SDR interfaces where no such exceptions are required.

So why use them ?
What's the benefit of using virtual clocks when constraining SDR interfaces ?

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4 Replies
viviany
Xilinx Employee
Xilinx Employee
364 Views
Registered: ‎05-14-2008

I don't think virtual clock is a must when constrainting the SDR or DDR interface.

Using virtual clock is one of the methods of I/O constraints.

For me, I prefer the method given in Vivado language template.

It sorts the templates based on the types of the interfaces.

Once you match your design interface with one of the templates, you can use the constraint examples in the template directly.

-vivian

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shaikon
Voyager
Voyager
352 Views
Registered: ‎04-12-2012

Thanks,

But can you please answer the original question ?

What are the benefits of using a Virtual Clock when constraining SDR interfaces ?

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viviany
Xilinx Employee
Xilinx Employee
347 Views
Registered: ‎05-14-2008

Could be a relatively natrual thingking of adding constraints for the I/O interface, since the launching clock in input delay and capturing clock in output delay are clocks that do not exist in the current design.

Just my two cents.

-vivian

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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shaikon
Voyager
Voyager
327 Views
Registered: ‎04-12-2012

Can someone please add more information on this ?

When dealing with SDR interfaces - What are the benefits of using a virtual clock as reference opposed to the real clock ? 

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