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Registered: ‎06-13-2011

Virtex 5 ISERDES to OSERDES data and clock sync problem

We are running ISE 14.1 running on Windows vista using the Xilinx programmer to send a bit file to part xc5vlv50-1ff1153 on a test board with a differential global clock coming in at 400 Mhz and differential data signal coming in at 100mhz . The VHDL program bufs the differential clock into single ended and then I use a DCM_ADV to create two output clocks on CLK0 and CLKDIV and a BUFG to create the input clock to a 1:4 ISERDES which then goes into an 4:1 OSERDES.  The problem we have with a simple 1:4 DDR MEMORY iserdes to 4:1 OSERDES DDR shows 'ghosting'  on the oserdes output as if the clock is on centered on the data using an oscilloscope.


I have tested with looking at the 4 outputs from the ISERDES and the signals are clean as is the OSERDES when I hardcode the 4 inputs in the code directly and look at the output.


So I guess my questions are:


How do we guarantee that oserdies data and clock are synchronized to the iserdies data?


how do we also guarantee that the oserdies data input is synced to the clock when we push either rtl data or memory data?


I have been reading UG190 to see if I am missing something else - perhaps an BUF between the ISERDES and OSERDES? Maybe there is another user guide to reference that addresses this?


Thank you,





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