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424 Views
Registered: ‎03-12-2020

Vivado FIFO Timing constraints are not met

Hello. 

I am trying to delay 200 CLK an 8-bit signal using a RAM as a FIFO.

(CLK=50 MHz)

This RAM has a read address different than the write address and uses only one clock Signal.

This is my VHDL Code:

 

 ------------------------------------------------------------VHDL CODE------------------------------------------

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;

entity FIFO_Timing is
    Generic (
    n_Delay :  integer := 8; --Bits to represent Total_Delay
    Total_Delay : integer := 200;
    m: integer :=9 --Size of Di
    );
    Port (
           RST : in  STD_LOGIC;
           CLK : in  STD_LOGIC;
           WR : in  STD_LOGIC;
           RD : in  STD_LOGIC;
           Di : in  STD_LOGIC_VECTOR(m-1 downto 0);
           Do: out  STD_LOGIC_VECTOR(m-1 downto 0)
    );
end FIFO_Timing;

architecture Behavioral of FIFO_Timing is
Signal Delay_Vector : std_logic_vector (n_Delay-1 downto 0);
--FIFO Signals
Signal ADW,ADR : std_logic_vector(n_Delay-1 downto 0) := (others=>'0');
Type RAMtype is array (0 to Total_Delay-1) of std_logic_vector(m-1 downto 0);
Signal MEM : RAMtype  := ( others=>(others=>'0') );
Begin

Delay_Vector <= std_logic_vector(to_unsigned(Total_Delay-1, Delay_Vector'length));

process(CLK)
begin
if rising_edge(CLK) then
if (WR='1') then
MEM(to_integer(unsigned(ADW))) <= Di;
end if;
Do <= MEM(to_integer(unsigned(ADR)));
end if;
end process;


process(RST,CLK)
begin
if RST='1' then
ADW <= (others=>'0');
ADR <= (others=>'0');
elsif rising_edge(CLK) then
if WR='1' then
   if ADW = Delay_Vector then
       ADW <= (others=>'0');
   else
        ADW <= std_logic_vector(unsigned(ADW)+1);
   end if;
else
    ADW <=(others=>'0');
end if;
if RD='1' then
    if ADR = Delay_Vector then
        ADR <= (others =>'0');
    else
        ADR <= std_logic_vector(unsigned(ADR)+1);
    end if;
else
   ADR <=(others=>'0');
end if;
end if;
end process;

end Behavioral;

I am using a 50 MHZ clock (CLK) signal. Using this Clock Constraint:

 

 

set_property PACKAGE_PIN P15 [get_ports CLK]
set_property IOSTANDARD LVCMOS33 [get_ports CLK]
create_clock -period 20.000 -name sysClk -waveform {0.000 10.000} -add [get_ports CLK]

I got the next results 

------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     17.623        0.000                      0                   32       -0.056       -0.108                      3                   32        9.500        0.000                       0                    19  


Timing constraints are not met.

 

Can somebody Help me to identify where the problem is?

PS: I already tried placing Registers in RD, WE, Di input signals and Do output signal, but it didn't work.

 

 

 

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6 Replies
Highlighted
Voyager
Voyager
413 Views
Registered: ‎06-28-2018

Re: Vivado FIFO Timing constraints are not met

Hi @amparoblabla123 

I'm guessing this report was generated after synthesis and I believe the tools will fix those hold time violations during implementation.

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Highlighted
403 Views
Registered: ‎03-12-2020

Re: Vivado FIFO Timing constraints are not met

Hi, yes. This is a report Generated after Synthesis, actually this is a Place Timing Report (After running implementation), so this Constraints violations were not fixed.

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Highlighted
Voyager
Voyager
400 Views
Registered: ‎06-28-2018

Re: Vivado FIFO Timing constraints are not met

Hi @amparoblabla123 

There is not much you can do about hold violations. Selecting a different implementation strategy might help.

Edit: If you did not run route you should do it and generate a new report after it finishes.

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Highlighted
390 Views
Registered: ‎03-12-2020

Re: Vivado FIFO Timing constraints are not met

Thanks, I already tried changing:

Settings>>Project Settings>>Implementation>> Strategy>> Performance_ExtraTimingOpt

But Timing Constraint still not meeting.

Do you know any other implementation that might help?

 

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Highlighted
380 Views
Registered: ‎06-21-2017

Re: Vivado FIFO Timing constraints are not met

Have you tried just using a FIFO from the IP catalog?

Highlighted
Adventurer
Adventurer
275 Views
Registered: ‎01-14-2009

Re: Vivado FIFO Timing constraints are not met

Is it because you use a non clk capable IO for clock input ?

Did you try different IO and see the affect on timing ?

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