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sprd_mgq
Observer
Observer
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Registered: ‎06-26-2018

Vivado IDE timing analysis issue.

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Hi,I have a question about Vivado timing analysis. On the page215 of UG906,a typical slack equation is given: Data Required Time (setup)= capture edge time  + destination clock path delay - clock uncertainty - setup time.

 

But,when I read the timing summary in my Vivado project,the setup time is plus not minus when derived the Data Required Time. Just like the graphic below.Why this conflict happened?

 

 

timing.png

 

 

 


 
 
 

 

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avrumw
Guide
Guide
1,049 Views
Registered: ‎01-23-2009

The setup time of the flip-flop itself is -0.044ns (slightly negative).

 

When the timing report subtracts a negative number, the two minus signs cancel, and it looks like addition.

 

Avrum

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avrumw
Guide
Guide
1,050 Views
Registered: ‎01-23-2009

The setup time of the flip-flop itself is -0.044ns (slightly negative).

 

When the timing report subtracts a negative number, the two minus signs cancel, and it looks like addition.

 

Avrum

View solution in original post

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sprd_mgq
Observer
Observer
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Registered: ‎06-26-2018

Thanks a lot for your reply. I'd like to accept your answer as a reasonable conclusion although it is hard for me to understand a negtive setup time.

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

Take a look at this similar post that discusses negative setup times.

 

Avrum

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