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valnyusa
Visitor
Visitor
10,206 Views
Registered: ‎10-02-2007

Vivado ILA integration in a block diagram project

Hi guys,

 

I'm using Vivado 2014.1 tool and try to get working ILA probe in my block diagram. So, I added to the diagram the ILA probe and compile it. It seems like there is a hidden clock input for sl_iport0_o[1]. It is always unconstrained. When I run Timing Constraints Wizard it proposes to enter Frequency or Period, due to undefined. I'm not sure what value has to be entered, but I entered. Even if I put something like 20 MHz or 50 MHz it it gives critical warning, that is no valid objects found for create constraint. What should be done in this case? Thank you in advance.

 

Val

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2 Replies
vuppala
Xilinx Employee
Xilinx Employee
10,192 Views
Registered: ‎04-16-2012

Hi,

Try below steps:
1. Open elaborated design
2. Search for the net for which you want to write the period constraint.
3. Copy its full name from "Net Properties" window
4. Write the period constraint in xdc file now.

Thanks,
Vinay
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valnyusa
Visitor
Visitor
10,160 Views
Registered: ‎10-02-2007

I changed a way for ILA integration in my block diagram project. This project is based on ZC706 board. Everything went well in point of synthesing, implementation and bit stream generating. I didn't insert any ILA IP and not instantiated in the top level vhd file, due to this file is read-only, it updates automatically when I change something in my block diagram. On the syntesised schematic I can see the probe and debugger cores, but not in the elaborated schematic. I generated the bit stream as well. Opened new hardware target and clicked to connect to the local server. It tries to connect to the server and seems like this effort becomes infinite. I have attached the block diagram here. What steps I missed? Thank you in advance.

 

Val

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