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Registered: ‎02-17-2020

Vivado Timing [38-436] warning

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Hi, 

I am trying to understand the reason behind this warning on Vivado: 

[Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.

I have a basic design with clocking_wizard and XADC IPs. I am generating a 104 MHz clock from the clk_wizard IP and using the 104 MHz clock for XADC's DCLK. In addition, I am using an ILA core to monitor the ADC signals.

Board: zybo Z7020

Constraints:
set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports sysclk];
create_clock -add -name sys_clk_pin -period 10.00 -waveform { 0 5 } [get_ports sysclk];

set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { vauxp15 }]; 
set_property -dict { PACKAGE_PIN J16 IOSTANDARD LVCMOS33 } [get_ports { vauxn15 }]; 

Kindly suggest measures to debug this warning on multiple clocks. Thanks!

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Registered: ‎01-22-2015

Re: Vivado Timing [38-436] warning

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bhaskara@tamu.edu 

Good job finding a solution and spending time to tell us about it !

However, did you tell the Clocking Wizard that the "Source" of the clock was a "Single ended clock capable pin" or a "Differential clock capable pin", as shown below?
Clk_Wiz_Source.jpg

If you did, then (as you know) the Clocking Wizard has already written the create_clock constraint for you and I recommend that you remove the create_clock constraint from your Vivado project's XDC file.

The trouble with leaving the create_clock constraint in the XDC file is that you (or someone else) might use it to change the frequency of the input clock - and this could cause problems with the MMCM.  That is, if you change frequency of the input clock then you must rerun the Clocking Wizard and tell the Wizard about the new frequency.  The Clocking Wizard will then configure its hardware (eg. VCO) correctly and write the correct create_clock constraint for you.

Mark

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Registered: ‎02-17-2020

Re: Vivado Timing [38-436] warning

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Found the reason here: https://forums.xilinx.com/t5/Timing-Analysis/Inter-Clock-paths-for-a-single-clock-and-a-couple-of-related/td-p/902926

Summary: Two constraints are declared for the clock - one coming from the clk_wiz IP and the other from top-level XDC. The -add option in the XDC creates a clock and IP as well creates an input clock and thereby a scenario of multiple_clocks warning in the Vivado.

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Registered: ‎01-22-2015

Re: Vivado Timing [38-436] warning

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bhaskara@tamu.edu 

Good job finding a solution and spending time to tell us about it !

However, did you tell the Clocking Wizard that the "Source" of the clock was a "Single ended clock capable pin" or a "Differential clock capable pin", as shown below?
Clk_Wiz_Source.jpg

If you did, then (as you know) the Clocking Wizard has already written the create_clock constraint for you and I recommend that you remove the create_clock constraint from your Vivado project's XDC file.

The trouble with leaving the create_clock constraint in the XDC file is that you (or someone else) might use it to change the frequency of the input clock - and this could cause problems with the MMCM.  That is, if you change frequency of the input clock then you must rerun the Clocking Wizard and tell the Wizard about the new frequency.  The Clocking Wizard will then configure its hardware (eg. VCO) correctly and write the correct create_clock constraint for you.

Mark

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Registered: ‎02-17-2020

Re: Vivado Timing [38-436] warning

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Thanks for the reply, Professor!

I declared the clocking wizard's source as a single-ended clock capable pin. I removed the create clock constraints as advised. I am able to run the implementation and generate bitstream file. However, I have got the following warnings (image attached):

1) Impl: set_bus_skew constraints
2) Bitstream: No routable loads for 25 nets
3) PS7 block required

Timing report does not indicate any failing endpoints and the no routable loads appear to be all related to debug hub (I used ILA core in my design). Do I have to worry about these warnings and how to get around them? 

Thanks! 

 

1.JPG
2.JPG
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Registered: ‎01-22-2015

Re: Vivado Timing [38-436] warning

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bhaskara@tamu.edu 

The general rule with the Xilinx tools is that “warnings” can be ignored.  However, “critical warnings” and “errors” must be addressed.

Here are thoughts on the warnings you are receiving:

[DRC RSTAT-10] No routable loads:  I am not familiar with the debug hub and these warnings.  However, <this> post has some guidance for you.

[Timing 38-436] There are set_bus_skew constraint(s) in this design:  set_bus_skew and set_max_delay-datapath_only constraints are used when multi-bit data (ie. a bus) makes a clock-domain-crossing (CDC) – see chapter 6 in UG903(v2019.1) for more information.  If you did not write any set_bus_skew constraints, then these constraints might have been automatically written when you setup the debug hub.

[DRC-ZPS7-1] PS7 block required:  The Processing System 7 (PS7) core helps to connect the PS and PL sides of your Zynq FPGA by managing things like the extended multiplexed I/O (EMIO), programmable logic I/O, and the AXI I/O groups.  For more information see Xilinx document, PG082.

Try removing the debug hub to see what effect is has on the list of warnings.

Mark

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Registered: ‎02-17-2020

Re: Vivado Timing [38-436] warning

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Thanks! Removing debug_hub eliminated the first two errors! I'll read about these warnings more as I need to include the ILA debug core and eliminate these errors!
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