Vivado: Timing Analysis of Latch based clock gating logic
My design consists of a latch based clock gating logic mapped to FPGA. I am targetting my design on Virtex 7 using Vivado.
The RTL for the latch based clock gating is as follows.
always @ (i_clk or i_enable_n)
begin : LATCH
enable_n_latch_r = i_enable_n;
// generate the gated clock using the latched enable
assign o_gclk = i_clk && !enable_n_latch_r;
The synthesis tool converts the destination flop to FDCE with the CE pin fed by the enable logic that is driven from HSTDM through LUT for combo logic as shown in attached report. The enable signal is fed from another FPGA through HSTDM logic used in order to reduce the pincount of the interface between the FPGA.
For the analysis of this issue, the core_clock is @26MHz and HSTDM logic works at 9xcore_clock = 234 MHz. Hence the core_clock period is 38.460ns and HSTDM clock period is 4.273ns
The timing analysis is done as follows. From the report, the capture edge reference is 38.460ns. The launch edge is one clock before the capture edge so its 38.460 - 4.273 = 34.187 ns.
There are clock compensation applied as MMCM components are used to generate the HSTDM and Core clocks.
I have attached the timing report of one of the datapath which is resulting in setup violations.
The tool is reporting a large data delay 20.544ns while the actual delay is 2.615ns of which logic 0.396ns (1.928%) route 2.219ns (10.800%)
It is also adding a time given to startpoint delay (17.929) due to presence of the latch hence the delay is calculated as (2.615 + 17.929ns=20.544ns) resulting in timing violation. This could be due to the reference of the falling edge of the clock sampling the latch (19.23ns) that does not fall within the time the data arrives at D input of the latch.
I tried to use a slower clock 10MHz but still I still observe slack due to the addition of time given to startpoint value. Any suggestions to resolve this issue?