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barrygmoss
Contributor
Contributor
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Registered: ‎03-20-2018

Vivado deleting constraints from non-target xdc files when setting up debug

I've repeatedly run into this problem using Vivado 2019.2. I've tried separating out my constraints into multiple XDC files and designating an XDC file with no user constraints as the target, but Vivado still seems to be going after my timing constraints in two other files. The result is a design that fails timing badly because one of the constraints sets up asynchronous clock groups. 

set_clock_groups -asynchronous -group [get_clocks o0II_4] -group [get_clocks -of_objects [get_pins flash_clk_gen_inst/inst/plle4_adv_inst/CLKOUT0]]


Now one factor that could be causing the problem is that this refers to a clock source buried inside encrypted logic from a 3rd party IP, but still Vivado should never modify user source and these constraints files are user source. To make matters worse, this isn't simply some redundant constraint (like the second pin placement on a differential signal) it's actually important and the implementation self-destructs without. 

The other constraints that Vivado regularly blows away in a silent bit of implementation suicide, are self_false_path constraints referring to gigabit transceivers in the encrypted IP. 

If Vivado detects a problem with constraints, it should raise a warning or an error as appropriate, but not silently modify user files. 

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hemangd
Moderator
Moderator
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Registered: ‎03-16-2017

@barrygmoss 

To narrow down your issue, let's do some checks. 

1. When you add this set_clock_groups command in tcl console directly after opening the implemented design, what error/warning you see? Or do you see no error/warning? Kindly confirm. If no messages appear then it gets passed then just reopen the timing summary and see the timing value difference. 

2. Can you check these clocks are present in the design by running get_clocks <clock_name>

3. Another simpler way to add timing exception is - to use timing constraint wizard. Can you give it a try with it? Check this video for more info. on it. https://www.xilinx.com/video/hardware/using-vivado-timing-constraint-wizard.html

Also, check UG 903 for more info on it. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug903-vivado-using-constraints.pdf

 

Regards,
hemangd

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