10-09-2017 10:12 AM
I am using a USB chip that I am interfacing to an Artix device. I want to create some input/output constraints for it. The clock is 100 MHz. The USB chip output parameters are 3ns setup/ 3.5ns hold (rising edge of the clock). The USB chip input parameters are 2.3ns setup/3.8ns hold (rising edge of the clock). I did try to do this with the constraints wizard, but ended up with huge timing errors so I think I may have input something wrong. Any help appreciated.
10-09-2017 11:09 AM
Input and output delay constraints will be find out on based on what interface you are using with fpga to upstream/downstream device and how your data is aligned with the clock. You can select source synchronous or system synchronous interface as per your requirement. And select one of the relation between data and clock which is edge aligned or center aligned as per your requirement.
After deciding your requirements you can use language templates of input delay and output delay constraints from Vivado flow navigator from where you can calculate necessary values to evaluate i/o delay constraints. (As shown in below snapshot.)
By using Setup and hold values you can evaluate other values as per your requirement which is mentioned in the language templates.
10-10-2017 01:43 AM
I have had a look at the templates. The clock from the USB device comes into a MMCM. I then use a this clock as the 100MHz clock. So in the language template I guess I would use source sync, edge aligned (MMCM)?
10-11-2017 11:45 PM - edited 10-11-2017 11:46 PM
As per your requirement, yes you can go for edge aligned ( Clock with MMCM). And use that respective language template.
There are two different captures at the receiving device ( FPGA). MMCM Capture and Direct Capture ( directly F/F).
You can also go through this thread which shows the difference between MMCM capture vs Direct Capture & also edge aligned vs center aligned.
Mark this post as accepted solution, if it has resolved your issue.