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Scholar
Scholar
2,933 Views
Registered: ‎04-27-2010

Vivado input/output delay constraints

Hi

 

I am using a USB chip that I am interfacing to an Artix device. I want to create some input/output constraints for it. The clock is 100 MHz. The USB chip output parameters are 3ns setup/ 3.5ns hold (rising edge of the clock). The USB chip input parameters are 2.3ns setup/3.8ns hold (rising edge of the clock). I did try to do this with the constraints wizard, but ended up with huge timing errors so I think I may have input something wrong. Any help appreciated.

Thanks

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Moderator
Moderator
2,915 Views
Registered: ‎03-16-2017

Hi @beandigital,

 

Input and output delay constraints  will be find out on based on what interface you are using with fpga to upstream/downstream device and how your data is aligned with the clock. You can select source synchronous or system synchronous interface as per your requirement. And select one of the relation between data and clock which is edge aligned or center aligned as per your requirement.

 

After deciding your requirements you can use language templates of input delay and output delay constraints from Vivado flow navigator from where you can calculate necessary values to evaluate i/o delay constraints.  (As shown in below snapshot.)

 

 

 

time.PNG

 

By using Setup and hold values you can evaluate other values as per your requirement which is mentioned in the language templates.

 

Regards,

hemangd

 

Regards,
hemangd

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Scholar
Scholar
2,905 Views
Registered: ‎04-27-2010

Thanks for the info.
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Scholar
Scholar
2,833 Views
Registered: ‎04-27-2010

I have had a look at the templates. The clock from the USB device comes into a MMCM. I then use a this clock as the 100MHz clock. So in the language template I guess I would use source sync, edge aligned (MMCM)?

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Moderator
Moderator
2,809 Views
Registered: ‎03-16-2017

Hi @beandigital,

 

As per your requirement, yes you can go for edge aligned ( Clock with MMCM). And use that respective language template.

 

FYI: 

 

There are two different captures at the receiving device ( FPGA). MMCM Capture and Direct Capture ( directly F/F).

 

You can also go through this thread which shows the difference between MMCM capture vs Direct Capture & also edge aligned vs center aligned.

https://forums.xilinx.com/t5/Timing-Analysis/difference-between-center-edge-mmcm-and-edge-direct-allignments/td-p/645400

 

 

Regards,

hemangd

 

--------

Mark this post as accepted solution, if it has resolved your issue.

 

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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