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elvisjohndowson
Explorer
Explorer
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Registered: ‎12-30-2008

Vivado pre-implementation timing analysis and closure techniques

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Hi,

 

Q01: Are there any pre-implementation timing analysis and closure techniques that I can apply, upon finding end-points with a negative slack in my design, as shown in the attached screenshot, for axi_dma_1?

 

201312260030-Vivado-2013.2-Pre-Implementation-Timing-Analysis.png

 

UG938 - Vivado Design Suite Tutorial - Design Analysis and Closure Techniques only talk about post-implementation timing analysis and closure, not for pre-implementation. The UltraFast design methodology also talks about fixing timing slack early on in the design.

 

Q02: Where can I find tutorial or resources on how to fix timing problems during static timing analysis?

 

Thanks in advance!

 

Regards,

 

Elvis Dowson

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elvisjohndowson
Explorer
Explorer
14,481 Views
Registered: ‎12-30-2008

Hi,

       I found the guidances in the UltraFast Design Methodology to be useful.

 

Xilinx UltraFast Design Methodology

 

 

UG938 - Vivado Design Suite Tutorial - Design Analysis and Closure Techniques v2013.4 was pretty useful for exploring the timing analysis and performing place and route features of Vivado, but it leaves one wanting for more, in terms of additional exercises.

 

Regards,

 

Elvis Dowson

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graces
Moderator
Moderator
8,629 Views
Registered: ‎07-16-2008

The timing model from synthesis through implementation is common, it's just in synthesized design, the routing delay is estimated and the logic will possibly be optimized or changed in implementation.

 

So in post-synthesis result, we recommend that you focusing on validating the constraints, whether there're any unrealistic requirement (e.g. 200ps), whether there're missing CDC constraints, etc.

If the violation is caused by high levels of logic, consider optimizing HDL code prior to implementation.

 

Please review section "Baselining the Design" in UG949 (Ultrafast Design Methodology Guide).

 

For closure techniques, please have a look at UG906.

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elvisjohndowson
Explorer
Explorer
14,482 Views
Registered: ‎12-30-2008

Hi,

       I found the guidances in the UltraFast Design Methodology to be useful.

 

Xilinx UltraFast Design Methodology

 

 

UG938 - Vivado Design Suite Tutorial - Design Analysis and Closure Techniques v2013.4 was pretty useful for exploring the timing analysis and performing place and route features of Vivado, but it leaves one wanting for more, in terms of additional exercises.

 

Regards,

 

Elvis Dowson

View solution in original post

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