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Vivado quality control feedback

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Voyager
Posts: 322
Registered: ‎04-21-2014
Accepted Solution

Vivado quality control feedback

The clock interaction report (report_clock_interaction) is a great tool used for identifying, reporting on, and properly constraining bot synchronous and asynchronous clock domain crossings.  However, even for a small design, the number of clock domains can be daunting to look at graphically.  For example, the attached image is for a relatively small design of a small DSP subsystem with PL DMA that can access PS DDR3 and MIG DDR3 on a ZX706 card.  Given the matrix nature of the report, the complexity of the report, and size of the matrix, goes up as a square law. While the vertical and horizontal scroll bars are useful for a large number of clocks that exist on many real world designs that are still modest in size, the interface is still not useful on such designs.

 

Consequently, I make the following suggestions, with the hope that they be passed on to the development team management for consideration.

 

Suggestions:

 

1. Sort the top to bottom source clocks and left to right destination clocks by number of paths.  The current sorting appears to be alphabetical.  (Or create a link on the source clocks / destination clocks that allows the user to change the sorting).

 

2.  Add command line options to reduce the number of clocks analyzed in the report (or at least the number of clocks displayed in the GUI panel) .  This will be useful while doing design review on certain parts of the heiracrcy.  E.g., -group {CLKA CLKB CLKC CLKD}.  You could add a clock selector wizard to the (tools->timing->report clock interaction) eventually.

 

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
report_clock_interaction_zc706.jpg

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Moderator
Posts: 4,634
Registered: ‎08-01-2008

Re: Vivado quality control feedback

thanks for your suggestions . Please provide your feedback here as well
It will routed to correct team

here is link
https://www.xilinx.com/about/feedback/website-feedback.html
Thanks and Regards
Balkrishan
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Moderator
Posts: 4,634
Registered: ‎08-01-2008

Re: Vivado quality control feedback

thanks for your suggestions . Please provide your feedback here as well
It will routed to correct team

here is link
https://www.xilinx.com/about/feedback/website-feedback.html
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
Voyager
Posts: 322
Registered: ‎04-21-2014

Re: Vivado quality control feedback


balkris wrote:
thanks for your suggestions . Please provide your feedback here as well
It will routed to correct team

here is link
https://www.xilinx.com/about/feedback/website-feedback.html

Thanks @balkris

 

The ball is in your hands now.  :)   It wasn't website feedback anyway.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
Moderator
Posts: 1,421
Registered: ‎01-16-2013

Re: Vivado quality control feedback

Hi @morgan198510

 

I have filed the enhancement CR#972628.

 

Thanks,
Yash

Voyager
Posts: 322
Registered: ‎04-21-2014

Re: Vivado quality control feedback

Okay, awesome, great.  Thanks Yash!

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***