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Explorer
Explorer
383 Views
Registered: ‎04-12-2012

Vivado's default timing analysis corners

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Hello,

I know that Vivado does timing analysis based on 4 Voltage / Temperature corners.

Can you point me to a document that lists the exact values for these corners ?

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Historian
Historian
339 Views
Registered: ‎01-23-2009

Re: Vivado's default timing analysis corners

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The answer is simple - the worst ones.

Each speed grade and commercial grade of an FPGA is specified to operate over a specific set of voltage/temperature ranges. The static timing anlysis is done at the two "voltage/temperature points within the legal range of operating conditions that produces the fastest and slowest cell delays". These are referred to as the [SLOW_MAX] and [FAST_MIN] timing corners.

For on-chip-variation, the tool also uses two other corners [SLOW_MIN] and [FAST_MAX]. The definition of these is more nebulous - the best I can come up with is "[SLOW_MIN] is the fastest a cell can be on the same die with at least one cell that is at [SLOW_MAX]" and "[FAST_MAX] is the slowest a cell can be on the same die with at least one cell that is at [FAST_MIN]"

There is actually no mention of what temperature/voltage combination any of these are. In fact, in modern technologies, the temperature curve is no longer monotonic - it is not longer (necessarily) true that the [SLOW_MAX] timing characteristic occurs at the highest legal die temperature (which used to be true in older/larger CMOS technologies).

However, I suspect that where you are trying to go with this is "can I use any kind of derating". For example if you are using a commercial device (which has a maximum die temperature of 85C) and you are ensuring that the die will never exceed 70C in your environment, can you take advantage of this fact. The answer is no. Xilinx does not provide any information on derating, and has no mechanism for doing timing analysis with derating - timing can be and must be done only at the PVT extremes described above.

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Scholar drjohnsmith
Scholar
374 Views
Registered: ‎07-09-2009

Re: Vivado's default timing analysis corners

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This has come up a few times,

my guess is your being lead by an ASIC background,

   but in the FPGA, xilxin have doen al th ework for you !

 

have a look here

https://forums.xilinx.com/t5/Timing-Analysis/multi-corner-timing-analysis/td-p/64786

https://forums.xilinx.com/t5/Timing-Analysis/Best-case-worst-case-timing-reports/td-p/61374

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Explorer
Explorer
358 Views
Registered: ‎04-12-2012

Re: Vivado's default timing analysis corners

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I asked : "What temperature values does Vivado use for the 4 corners of timing analyis?" 

You answered:

"but in the FPGA, xilinx have done all the work for you !"

Done what work for me ? I'm not looking for anything to be done.

I had a simple "knowledge" question - I'll ask again:

What temperature and voltage does Vivado use for the 4 corners of the timing analysis it performs ? 

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Historian
Historian
340 Views
Registered: ‎01-23-2009

Re: Vivado's default timing analysis corners

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The answer is simple - the worst ones.

Each speed grade and commercial grade of an FPGA is specified to operate over a specific set of voltage/temperature ranges. The static timing anlysis is done at the two "voltage/temperature points within the legal range of operating conditions that produces the fastest and slowest cell delays". These are referred to as the [SLOW_MAX] and [FAST_MIN] timing corners.

For on-chip-variation, the tool also uses two other corners [SLOW_MIN] and [FAST_MAX]. The definition of these is more nebulous - the best I can come up with is "[SLOW_MIN] is the fastest a cell can be on the same die with at least one cell that is at [SLOW_MAX]" and "[FAST_MAX] is the slowest a cell can be on the same die with at least one cell that is at [FAST_MIN]"

There is actually no mention of what temperature/voltage combination any of these are. In fact, in modern technologies, the temperature curve is no longer monotonic - it is not longer (necessarily) true that the [SLOW_MAX] timing characteristic occurs at the highest legal die temperature (which used to be true in older/larger CMOS technologies).

However, I suspect that where you are trying to go with this is "can I use any kind of derating". For example if you are using a commercial device (which has a maximum die temperature of 85C) and you are ensuring that the die will never exceed 70C in your environment, can you take advantage of this fact. The answer is no. Xilinx does not provide any information on derating, and has no mechanism for doing timing analysis with derating - timing can be and must be done only at the PVT extremes described above.

Avrum

View solution in original post