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Adventurer
Adventurer
15,695 Views
Registered: ‎12-02-2010

Vivado - set_input_delay and BUFGMUX

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I am trying to come up to speed on proper constraint use in Vivado.  My design is an Artix-7 and I'm using Vivado 2014.1.

 

I accept data from an external device on pins clk1 and data1.  I know these PCB trace lengths are matched to within +/- 10 mils so skew is in the low picosecond range.  The max operating frequency of this interface is 165 MHz (6.06 nS) and the datasheet for the external device gives TDmin = 1.64 ns and TDmax = 4.85 ns for data out relative to the clock.  Based on this information I placed the following constraints in my design for this interface:

 

create_clock -period 6.06 -name clk1 [get_ports clk1]

set_propagated_clock clk1

 

set_input_delay -max 4.85 -clock clk1 [get_ports data1]

set_input_delay -min 1.64 -clock clk1 [get_ports data1]

 

So far so good?

 

The first thing I do is register the data to improve timing from this point forward:

 

process(clk1)

begin

    if rising_edge(clk1) then

        data1_r <= data1;

    end if;

end process;

 

Now assume that I have a second asynchronous data source on signals clk2 and data2_r and I wish to be able to dynamically select between the two sources based on user input.  I use a BUFGMUX to select the clock, as follows:

 

inst_BUFGMUX : BUFGMUX_CTRL
port map (
    I0 => clk1,
    I1 => clk2,
    O => clk3,
    S => sel
);

 

I select between the two data sources as follows:

 

process(clk3)

begin

    if rising_edge(clk3) then

        if rising_edge(clk3) then

            if (sel = '0') then

                data3_r <= data1_r;

            else

                data3_r <= data2_r;

             end if;

        end if;

    end if;

end process;

 

What additional constraints are required to properly constrain this design?  Do I need to create a new clock constraint for clk3?  The frequency will be the higher of clk1 or clk2 but the phase will be off due to the delay through the BUFGMUX.

 

Thanks,

 

 

Michael

 

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Xilinx Employee
Xilinx Employee
25,081 Views
Registered: ‎11-28-2007

Re: Vivado - set_input_delay and BUFGMUX

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Hi Michael,

 

it depends on the constraint set on the output of the BUFGMUX.

If you just let the tool automatically propagate the clocks through the BUFGMUX, the tool will automatically create generated clock constraints on the output with the input clocks as base reference.

 

All the delays are included, which is good as this is the real life situation.

Don't forget that even if you design your paths properly, the relationship is fixed. If it doesn't meet timing, it will never meet timing as the delays don't drift like real asynchronous clocks. In other words, worst-case the registers always sample 0.5 instead of 0 or 1...

 

 

Best regards

Dries

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Scholar dwisehart
Scholar
15,690 Views
Registered: ‎06-23-2013

Re: Vivado - set_input_delay and BUFGMUX

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When using a BUFGMUX you have to do some extra work in the constraints file.

 

Do a search here on BUFGMUX and you will find notes on set_case_analysis:

http://forums.xilinx.com/t5/Timing-Analysis/Vivado-and-BUFGMUX-timing/m-p/444448

 

and

http://www.xilinx.com/support/documentation/sw_manuals/xilinx2013_4/ug903-vivado-using-constraints.pdf

 

Regards,

Daniel

 

Xilinx Employee
Xilinx Employee
15,669 Views
Registered: ‎08-02-2007

Re: Vivado - set_input_delay and BUFGMUX

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Hi,

 

There is an issue currently under investigation. I would recommend you to apply the set_case_analysis on the select line.

 

For the explanation part, refer to http://forums.xilinx.com/t5/Timing-Analysis/Vivado-and-BUFGMUX-timing/m-p/444448

 

--Hem

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Adventurer
Adventurer
15,637 Views
Registered: ‎12-02-2010

Re: Vivado - set_input_delay and BUFGMUX

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I have just gotten to the point of adding several clock muxes into my design and I'm getting implementation errors regarding BUFGMUX placement.  I don't recall having these issues with VIrrtex-5 or Virtex-6 designs - is this something new to Artix-7?  It looks like cascaded muxes need to be adjacent to each other in the FPGA in order to use dedicated cascade paths.  What kind of penalty can I expect if I override this using CLOCK_DEDICATED_ROUTE FALSE constraints?

 

Michael

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Xilinx Employee
Xilinx Employee
15,634 Views
Registered: ‎07-16-2008

Re: Vivado - set_input_delay and BUFGMUX

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Please have a look at 7series clocking guide, pg23, Table 1-1.

http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

 

BUFG can be used to directly drive adjacent BUFGs in same top/bottom half.

 

If you allow non-dedicated routing by applying CLOCK_DEDICATED_ROUTE = FALSE, the net delay between the cascaded BUFGs could be large, causing timing hazards.

 

BTW, this rule should also apply in V5 or V6. You didn't receive errors probably because in those targets, the tool was able to find a legal placement that satisfy the cascading rule.

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Xilinx Employee
Xilinx Employee
15,627 Views
Registered: ‎11-28-2007

Re: Vivado - set_input_delay and BUFGMUX

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@mellis wrote:

I have just gotten to the point of adding several clock muxes into my design and I'm getting implementation errors regarding BUFGMUX placement.  I don't recall having these issues with VIrrtex-5 or Virtex-6 designs - is this something new to Artix-7?  It looks like cascaded muxes need to be adjacent to each other in the FPGA in order to use dedicated cascade paths.  What kind of penalty can I expect if I override this using CLOCK_DEDICATED_ROUTE FALSE constraints?

 

Michael


Michael,

 

forgive me but your issue is not related to the subject of this thread.

In the future, please create new threads to discuss non-related issues.

If you want to continue your discussion, please also create a new thread.

 

 

Best regards

Dries

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Xilinx Employee
Xilinx Employee
15,626 Views
Registered: ‎11-28-2007

Re: Vivado - set_input_delay and BUFGMUX

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@htsvn wrote:

Hi,

 

There is an issue currently under investigation. I would recommend you to apply the set_case_analysis on the select line.

 

For the explanation part, refer to http://forums.xilinx.com/t5/Timing-Analysis/Vivado-and-BUFGMUX-timing/m-p/444448

 

--Hem


Hi Hem

 

I do not agree this is an issue.

This is expected behaviour with a known and documented solution. (see my post in that thread)

 

 

Best regards

Dries

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Adventurer
Adventurer
15,616 Views
Registered: ‎12-02-2010

Re: Vivado - set_input_delay and BUFGMUX

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graces,

 

Do the timing tools use the output of the BUFGMUX as the basis for timing from that point forward or they they still try to account for cascaded mux delays back to the source clock?  Whenever I use a BUFGMUX I always immediately register my data path into the new post-mux clock domain.  These registers must meet timing for the pre-mux clock plus the BUFGMUX delay, but everything downstream should only have to meet timing for the post-mux clock.

 

Thanks,

 

Michael

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Xilinx Employee
Xilinx Employee
25,082 Views
Registered: ‎11-28-2007

Re: Vivado - set_input_delay and BUFGMUX

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Hi Michael,

 

it depends on the constraint set on the output of the BUFGMUX.

If you just let the tool automatically propagate the clocks through the BUFGMUX, the tool will automatically create generated clock constraints on the output with the input clocks as base reference.

 

All the delays are included, which is good as this is the real life situation.

Don't forget that even if you design your paths properly, the relationship is fixed. If it doesn't meet timing, it will never meet timing as the delays don't drift like real asynchronous clocks. In other words, worst-case the registers always sample 0.5 instead of 0 or 1...

 

 

Best regards

Dries

--------------------------------------------------------------------------------------------------------------------
Please mark the Answer as "Accept as solution" if the information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented by clicking the star next to the post.

View solution in original post

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Adventurer
Adventurer
15,424 Views
Registered: ‎12-02-2010

Re: Vivado - set_input_delay and BUFGMUX

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I have started anther thread to continue this discussion:

 

http://forums.xilinx.com/t5/Timing-Analysis/Constraining-complex-clock-structures-in-Vivado/td-p/468286

 

Michael

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