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yky
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Registered: ‎07-17-2021

I checked the critical path in vivado, but I couldn't understand the naming rules of Netlist resources in timing summary, for example, there is no ins_out_reg in my module, but in the picture, you can see it.Please give me some help to understand the naming rules of Netlist resources.

-4a3bf70b59945313.png

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avrumw
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Registered: ‎01-23-2009

What does postfix "i_7_n_0" means?

Essentially nothing. 

We code in RTL - Register Transfer Language. This means we explicitly code the registers and the transfers between them. The registers are inferred by (normally non-blocking) assignments to a reg/logic/signal in a clocked block (and used outside the block). Pretty much everything else is the "transfers".

Each of these "transfers" is a combinatorial network that takes inputs from flip-flops and/or primary inputs of the device and generates outputs for flip-flops. This combinatorial network is what synthesis infers from the RTL code and then optimizes - it translates it to a network of LUTs and some other cells (carry chains, wide MUXes). This network is then optimized repeatedly to find a "good enough" implementation that meets the requirements (speed, area, power). During the inference and optimization cells may be added, merged, moved, reconnected, etc... During each optimization, these cells and the nets between them need to be named. The tool uses its own mechanisms for assigning these names, and maybe they even make sense to someone deeply involved in the synthesis algorithm, but to a "regular" user, the generally carry little information. Sometimes the basename tells you something about where the logic originally started, but not always. In general the only thing you can really understand about these paths (through these transfers) are where they start and where the end - the names of everything in between rarely gives any useful information.

Avrum

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avrumw
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Registered: ‎01-23-2009

I am pretty sure that says "lns_out_reg" (an L, not an I). It would be inferred when there is an assignment to the reg/signal "lns_out" in an always @(posedge clk) statement; synthesis always appends the _reg suffix to any flip-flop (or latch) it infers.

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yky
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Registered: ‎07-17-2021

What does postfix "i_7_n_0" means?

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avrumw
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Registered: ‎01-23-2009

What does postfix "i_7_n_0" means?

Essentially nothing. 

We code in RTL - Register Transfer Language. This means we explicitly code the registers and the transfers between them. The registers are inferred by (normally non-blocking) assignments to a reg/logic/signal in a clocked block (and used outside the block). Pretty much everything else is the "transfers".

Each of these "transfers" is a combinatorial network that takes inputs from flip-flops and/or primary inputs of the device and generates outputs for flip-flops. This combinatorial network is what synthesis infers from the RTL code and then optimizes - it translates it to a network of LUTs and some other cells (carry chains, wide MUXes). This network is then optimized repeatedly to find a "good enough" implementation that meets the requirements (speed, area, power). During the inference and optimization cells may be added, merged, moved, reconnected, etc... During each optimization, these cells and the nets between them need to be named. The tool uses its own mechanisms for assigning these names, and maybe they even make sense to someone deeply involved in the synthesis algorithm, but to a "regular" user, the generally carry little information. Sometimes the basename tells you something about where the logic originally started, but not always. In general the only thing you can really understand about these paths (through these transfers) are where they start and where the end - the names of everything in between rarely gives any useful information.

Avrum

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