I have a project where I use logic between two Axi Stream interfaces, in the signals ready and valid, as a form of enable mechanism between a FIFO and the 10 / 25G Ethernet Subsystem. This way I can ensure that the FIFO already has at least one complete frame to start sending.
The problem is that with this logic between some of the interface signals I have a negative WNS. Any tips? I've tried to reduce the clock frequency but it didn't solve anything.
It is always unclear if the person To get quality feedback, post your path report and/or a schematic of the failing path, including the clock(s) trace back to their source(s). How experienced are you at Static Timing analysis and Xilinx Design Constraints (STA/XDC)? Do you know how to handle asynchronous CDC (if that is an issue in your design)? Multi-cycle paths (probably not an issue but never can tell without seeing your timing report).
In the meantime, if you haven't already, you can try last mile strategies such as turning on retiming in synthesis, perfOptimized_high, and similar modifications to the implementation. But this might help if you are pretty close to meeting timing, but your builds may take longer.
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