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Contributor
Contributor
1,490 Views
Registered: ‎09-22-2017

Warning in synthesis, signal period is out of range ?

Hi

I have a little issue in my design, especially in my constraint file.
One input of my design is clock signal with a frequency of 2KHz.

 

As i used to do, i added a constraint to define my clock signal in a XDC file:

 

create_clock -period 500000.000 -name htr2k -waveform {0.000 250000.000} [get_ports htr2k]


When i launched the synthesis part on VIvado, i had the following warning:

 

 

WARNING: [Synth 8-681] value '500000000.0ps' out of range, cropping to '214748368.0ps' [D:/Projects/xxxx/constrs_1/new/constr_timings.xdc:4]

 

I also tried to set this constraint with the Vivado tool, but i've had the same warning.

Which part i missed or didn't understood?

 

Thanks for your help

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6 Replies
Xilinx Employee
Xilinx Employee
1,459 Views
Registered: ‎05-06-2008

Re: Warning in synthesis, signal period is out of range ?

Our timing engine has an upper limit at ~214us, so we can handle 500us.  In most cases that need a clock this slow, then use 200us.  

Contributor
Contributor
1,429 Views
Registered: ‎09-22-2017

Re: Warning in synthesis, signal period is out of range ?

But, i don't understand one point. If i have to set a period constraint of 200us for my signal @2Khz, can i have some synthesis, or implementation warning? Moreover what is the impact on timing analysis ?

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Historian
Historian
1,416 Views
Registered: ‎01-23-2009

Re: Warning in synthesis, signal period is out of range ?

2KHz is extremely slow for an FPGA. So slow that the tools don't even allow you to specify a constraint this slow.

 

The clock period specified to the tool informs the tool how much logic can be placed between two flip-flops running on the same clock. At 500,000ns you can put utterly immense amounts of logic on a path - so much so that any even remotely reasonable design will have tremendous amounts of slack. So "over-constraining" the design from 500,000ns to 200,000ns will likely have no impact on the synthesis, placement or routing.

 

The only thing you may have to worry about is if this 2KHz clock is related to some other clock - you need to make sure that the real relationship is maintained, or at least has the same characteristics. So, if you also have a 20KHz clock that is related to your 2KHz clock, then when you change the 2KHz clock to 5KHz, the 20KHz should change to 50KHz. This also overconstrains the 20KHz clock, but this is still so slow that it won't matter - it probably doesn't start mattering in most designs until you get into the 10MHz range (or higher).

 

But lastly, why do you have a 2KHz clock in your design? It is really unusual to have a clock that runs this slow. If this is for some very slow interface, then one usually oversamples the interface singals and operates at a much more reasonable clock rate...

 

Avrum

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Contributor
Contributor
1,407 Views
Registered: ‎09-22-2017

Re: Warning in synthesis, signal period is out of range ?

Hi, 

 

thanks for your explanations.

 

If i well understood, i can let my constrain, the impact is that tools will over-constraint paths (if it is necessary).

 

The clock system of my FPGA has a frequency of 80MHz. But, my customer, has a specific function which used this clock. He want to use this signal to  generate an other FPGA output. So yes, it is for slow interface. 

 

 

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Highlighted
Historian
Historian
1,391 Views
Registered: ‎01-23-2009

Re: Warning in synthesis, signal period is out of range ?

In most applications that look like this, one doesn't tend to use the slow clock as a clock, but instead "oversamples" the periodic signal and operates at the base clock, enabled by the oversampled periodic signal.

 

So if your clk_2khz comes in on a pin you would metastability harden it with two back to back flip-flops on the 80MHz domain

 

(* ASYNC_REG = "TRUE" *) reg clk_2khz_meta, clk_2khz_sync;

always @(posedge clk80)

begin
   clk_2khz_meta <= clk_2khz;
   clk_2khz_sync  <= clk_2khz_meta;
end

Now you would do a rising detector on this signal to generate an enable signal on the 80MHz domain that is asserted once every time clk_2khz_sync makes a 0->1 transition

 

reg old_clk_2khz_sync;
wire clk_2khz_en;

always @(posedge clk80)
  old_clk_2khz_sync <= clk_2khz_sync;

assign clk_2khz_en = clk_2khz_synq && !old_clk_2khz_sync;

Now everywhere you want something done "synchronous" to this 2khz clock you would do

 

always @(posedge clk80)
begin
  if (clk_2khz_en)
  begin
     <do your code here>
  end
end

 

All of this code will then run at 80MHz. The tools will assume that it actually needs to run at 80MHz, but if this is just a slow I/O protocol, having it run at 80MHz won't actually be a problem.

 

If you need to some serious work at this 2khz rate, then you can go and declare all these paths as multicycle

 

set_multicycle_path -from [get_cells <all_ffs_that_use_clk_2khz_en>] -to get_cells [<all_ffs_that_use_clk_2khz_en>] <N>

set_multicycle_path -from [get_cells <all_ffs_that_use_clk_2khz_en>] -to get_cells [<all_ffs_that_use_clk_2khz_en>] -hold <N-1>

 

Where N is any reasonably large number less than 80MHz/2KHz. Practically anything larger than 4 or so won't matter - you could, for example, set it to 16 (and hence 15 for the hold), which will give plenty of time for almost anything you are trying to do. You could, of course, set it to 40000, but that would likely run into the same problem you are already experiencing...

 

Avrum

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Contributor
Contributor
1,340 Views
Registered: ‎09-22-2017

Re: Warning in synthesis, signal period is out of range ?

Thanks a lot.


You have well understood my design. Yes, i use a synchronisation mechanism to oversample my 2kHz clock in my 80MHz design. And then, of course, i only use this version of the signal.

 

I will look to the multicycle constraint you described. However, as you said, i'm using this signal for a specific function, but not some serious one.

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