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Explorer
Explorer
303 Views
Registered: ‎03-08-2018

What is the benefits on negedge clock with FIFO access?

I'm trying to understand about negedge clk in STA point of view.

 

This is the FIFO access verilog code, you can see the negedge when FIFO read,

I'm confused that what kind of benefits are in always@(negedge clk) instead always@(posedge clk)?

 

always@(negedge clk_out_0, negedge reset_n)begin
    if(reset_n == 1'b0)
        data_out2 <= 8'd0;
    else begin
        data_out2 <= fifo_valid ? fifo_out : 8'b0;
    end
end 
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5 Replies
Scholar dpaul24
Scholar
295 Views
Registered: ‎08-07-2014

Re: What is the benefits on negedge clock with FIFO access?

@love119,

I'm confused that what kind of benefits are in always@(negedge clk) instead always@(posedge clk)?

Nothing!

A digital logic design should be working only on either posedge clk or negative clock. Not both.

If you are using always@(negedge clk) in your verilog module, use the same throught the design or associated designs. Important is not to use a mix, in FPGA, strictly one edge.

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Explorer
Explorer
281 Views
Registered: ‎03-08-2018

Re: What is the benefits on negedge clock with FIFO access?


@dpaul24 wrote:

@love119,

I'm confused that what kind of benefits are in always@(negedge clk) instead always@(posedge clk)?

Nothing!

A digital logic design should be working only on either posedge clk or negative clock. Not both.

If you are using always@(negedge clk) in your verilog module, use the same throught the design or associated designs. Important is not to use a mix, in FPGA, strictly one edge.


@dpaul24 As I know If you are writing on a posedge, reading would be useful on a negedge. That would save one full clock cycle on a read operation. If you don't have as much as timing margin. this is to be a good solution.

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Scholar dpaul24
Scholar
264 Views
Registered: ‎08-07-2014

Re: What is the benefits on negedge clock with FIFO access?

@love119,

Two reasons not to write RTL code using both edges:

1> You are just making your life more difficult than it needs to be... especially where timing closure is concerned (developing accurate constraints is difficult). You can easily make this design operate on rising edge only.

2. Due to FPGA structure. Only IDDRs (which is a FPGA primitive) can sample the input on both edges of the clock, but puts out the result on two different outputs of the IDDR (Q1 and Q2) - not the same output. These IDDRs (which are very limited in numbers) are only located at the FPGA/chip physical boundaries, not throughout the FPGA fabric.

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Explorer
Explorer
253 Views
Registered: ‎03-08-2018

Re: What is the benefits on negedge clock with FIFO access?

That's nothing about the reason. You didn't close to the answer about the topic. it's not the problem whether easy life or not. plz considerate your reply next time before reply to someone.
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Scholar dpaul24
Scholar
245 Views
Registered: ‎08-07-2014

Re: What is the benefits on negedge clock with FIFO access?

That's nothing about the reason. You didn't close to the answer about the topic

Sorry I didn't understand the meaning of these two sentences.

 

it's not the problem whether easy life or not.

Ok, go ahead and work with STA to get a successful timing closure using both clock edges in your design. I have showed you the disadvantages, now it is your wish.

1> I would recommend you read the post, the answer from avrumw - https://forums.xilinx.com/t5/General-Technical-Discussion/Negative-edge-FFs/td-p/782105

2> Another example where someone wnated to use rising and falling edges and was told why it is a bad idea, read it COMPLETELY and UNDERSTAND it - https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Dual-edge-counter-not-woking-on-Spartan/td-p/237574

All I want to say that you are thinking on the wrong line. Theoritically you are correct, but practically it is not done................writing with the +edge and reading with the falling edge.

 

plz considerate your reply next time before reply to someone.

Again I didn't understand this sentence. Why do you think my answer is inconsiderate?

 

 

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