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Adventurer
Adventurer
186 Views
Registered: ‎11-18-2017

What is the best way to improve negative slack?

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Hello.

 

I'm designing a logic with 500 MHz clock.

Since the clock is fast, it is hard to avoid time violation (there are numerous paths with negative slack).

To improve slack, I am dividing combinational logics with FFs.

By such method, the slack improves but the latency and resource usage increases.

Are there any design tips to improve negative slacks?

 

Thanks for your help.

 

 

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Highlighted
140 Views
Registered: ‎01-22-2015

Re: What is the best way to improve negative slack?

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@kimjaewon 

I find that timing analysis problems (ie. negative slack) generally fall into one of the following categories:

  • Too Much Processing: We tried to do too much processing of the signal inside an HDL clocked process.
  • Clock Crossings: We are calculating a signal in a clocked process that uses clock, CLK1, and then using the signal in another clocked process that uses clock, CLK2 – and CLK1 is not equal to CLK2.  This is also called crossing a signal from the CLK1 clock-domain into the CLK2 clock-domain.
  • FPGA Input/Output (I/O) Problems: Data coming into or going out of the FPGA has improper skew with respect to the FPGA I/O clock.

FPGA IO problems are the most difficult to solve and often require expert help.

Clock crossing problems are often easily corrected with synchronizer circuits and by writing timing exceptions.

Too-much-processing problems are often corrected by (as you say) pipelining (ie. using registers to break-up large amounts of combinational logic).

Xilinx gives tips for resolving timing analysis problems (aka. achieving timing closure) in chapter 7 of UG906 and in chapter 5 of UG949.

Other tips for resolving timing analysis problems include:

  • Constants: if part of your HDL is calculating the same thing over-and-over then change the HDL to calculate it once and store the result as a constant
  • Look-Up Tables: if part your HDL is calculation something that can have only a few values, then change the HDL to calculate these values only once and store them as constants in an array (aka look-up table).
  • Parallel Processing: If your HDL can be separated into two separate processes that don’t interact, then you can run them in parallel (rather than sequentially).  That is, two parallel processes running at 250MHz may finish in the same amount of time as one process running sequentially at 500MHz.

Cheers,
Mark

3 Replies
Scholar dpaul24
Scholar
176 Views
Registered: ‎08-07-2014

Re: What is the best way to improve negative slack?

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@kimjaewon,

To improve slack, I am dividing combinational logics with FFs.

That's what we all do to improve TNS.

 

By such method, the slack improves but the latency and resource usage increases.

You cannot help it.

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Xilinx Employee
Xilinx Employee
163 Views
Registered: ‎05-22-2018

Re: What is the best way to improve negative slack?

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Hi @kimjaewon ,

From tool end you can try the Resolving Hold Violation flow topic as mentioned in below UG link and check whether it helps:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug1292-ultrafast-timing-closure-quick-reference.pdf

Thanks,

Raj

Highlighted
141 Views
Registered: ‎01-22-2015

Re: What is the best way to improve negative slack?

Jump to solution

@kimjaewon 

I find that timing analysis problems (ie. negative slack) generally fall into one of the following categories:

  • Too Much Processing: We tried to do too much processing of the signal inside an HDL clocked process.
  • Clock Crossings: We are calculating a signal in a clocked process that uses clock, CLK1, and then using the signal in another clocked process that uses clock, CLK2 – and CLK1 is not equal to CLK2.  This is also called crossing a signal from the CLK1 clock-domain into the CLK2 clock-domain.
  • FPGA Input/Output (I/O) Problems: Data coming into or going out of the FPGA has improper skew with respect to the FPGA I/O clock.

FPGA IO problems are the most difficult to solve and often require expert help.

Clock crossing problems are often easily corrected with synchronizer circuits and by writing timing exceptions.

Too-much-processing problems are often corrected by (as you say) pipelining (ie. using registers to break-up large amounts of combinational logic).

Xilinx gives tips for resolving timing analysis problems (aka. achieving timing closure) in chapter 7 of UG906 and in chapter 5 of UG949.

Other tips for resolving timing analysis problems include:

  • Constants: if part of your HDL is calculating the same thing over-and-over then change the HDL to calculate it once and store the result as a constant
  • Look-Up Tables: if part your HDL is calculation something that can have only a few values, then change the HDL to calculate these values only once and store them as constants in an array (aka look-up table).
  • Parallel Processing: If your HDL can be separated into two separate processes that don’t interact, then you can run them in parallel (rather than sequentially).  That is, two parallel processes running at 250MHz may finish in the same amount of time as one process running sequentially at 500MHz.

Cheers,
Mark