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jlarin
Adventurer
Adventurer
14,036 Views
Registered: ‎06-07-2012

What is the minimal timing delay (how fast can a part be).

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Hi,

A long time ago, I needed to know how fast an output can be (from part to part).  This was needed for a hold time check on an external interface.  I remember finding somewhere on Xilinx web site that the fastest part can have a delay as fast as 25% of the minimal delay of the fastest speed grade of that part.

 

The 4x factor (25%) is coming from the variations from Process, Voltage and Temperature.  The fastest speed grade is because the FPGA is tested to meet timing from a specific speed/temperature grade, but you could get parts from faster bin without knowing it. 

 

I have been looking for that information on Xilinx web site and I can't find anything.  Have I imagined all this?

 

Best Regards,

 

jf

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driesd
Xilinx Employee
Xilinx Employee
22,386 Views
Registered: ‎11-28-2007

Hi Jf,

 

I thought you accepted the word of Xilinx employee as proof and documentation? ;)

 

as far as I know, we don't make this direct statement anywhere in our documentation or an (external) answer records.

There is however an internal answer record with that information.

 

Indirectly, you could tell from the delay numbers in our datasheet:

screenshot_002.jpg

As you can see (1), for hold, even for the slowest speedgrade, the fastest process is used for characterization. This is because indeed the slowest speedgrade devices could actually be the fastest process.

 

The reason why we do this is simple: it would not be economical to build up a stock-pile of higher/highest speedgrade devices, just in case we would get an order in the future. We manufacture to fulfill demand. Typically, the slowest speedgrades are the cheapest and the best selling. Higher speedgrades are less frequent and therefor more expensive to reduce the demand.

 

In addition, if you don't take my word, here are a few other threads with the same question:

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex5-speedgrade-questions/m-p/68934

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex-5-Speed-Grades/m-p/158502

 

 

Best regards

Dries

 

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driesd
Xilinx Employee
Xilinx Employee
14,035 Views
Registered: ‎11-28-2007

Hi jf,

 

what Xilinx tools are you using? ISE or Vivado?

 

In ISE, you can use:

trce -s min

 when generting the timing report or "speedprint" to list all timing parameters.

 

 

In Vivado, you can alter the timing analysis corner using the following TCL command:

config_timing_corners -corner Fast

Vivado does not have a speedprint equivalent command for 7-series. You still need to use the ISE speedprint tool.

 

 

Best regards,

Dries

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jlarin
Adventurer
Adventurer
14,029 Views
Registered: ‎06-07-2012

@driesd wrote:

Hi jf,

 

what Xilinx tools are you using? ISE or Vivado?

 


Hi Dries,

Thank you for looking at this. Right now I am using ISE but I have to jump to Vivado very soon as we are going to 7-series FPGA. 

 

However, my actual problem isn't to figure out what the timing is.  I design my FPGA in ways that I am not dependant on the minimal clock-to-out timing, so if I get a faster part, the design still work by design, not by luck.  My concern right now is: can I buy -3 (faster) speed grade parts instead of slower -2 speed grade device. This is only to help buyer who sometime cannot find -2 parts but can find -3 parts.  My argument is: my design MUST be able to tolerate faster parts and any design that does not tolerate faster parts IS A BAD design.  I am looking for documentation to support that affirmation.

 

Do you know any "official" documentation that explains that (User Guide, Application Note, Answer Record or Forum post from Xilinx Employee)?

 

Thank you,

 

jf

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gszakacs
Professor
Professor
14,025 Views
Registered: ‎08-14-2007

The tools already take into account the process variance between speed grades when computing the minimum delay times.  i.e. if you're not using the fastest speed grade, the minimum delay is still computed using minimum delays for the fastest speed grade.  This was not done intentionally to let you upgrade to a faster part, but it works for that, too.  The real reason is that parts are not "binned" but tested to order.  So a part that was tested to meet speed grade 2 may actually meet speed grade 3.  In fact this is more likely as the parts mature and the production yield for higher speed grade goes up well beyond the demand for that grade.

-- Gabor
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driesd
Xilinx Employee
Xilinx Employee
14,021 Views
Registered: ‎11-28-2007

Hi ,

 

I can confirm what Gabor is writing: a -2 speegrade meets or exceeds the -2 speed requirements.

However, it can be any faster part as well.

 

Make sure you buy through an Authorized Xilinx distributor. Otherwise you have no guarantee on the quality and the devices might actually be a lower-speed part that is re-marked.

 

 

Best regards

Dries

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jlarin
Adventurer
Adventurer
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Registered: ‎06-07-2012

Hi,

 

I realize now that the document is mis-leading.  I am not looking for how fast the device can go, or where I should buy the parts.  I already know that.  What I am looking for is not the information, is it the documentation that proves it.

 

Thank you,

 

jf

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driesd
Xilinx Employee
Xilinx Employee
22,387 Views
Registered: ‎11-28-2007

Hi Jf,

 

I thought you accepted the word of Xilinx employee as proof and documentation? ;)

 

as far as I know, we don't make this direct statement anywhere in our documentation or an (external) answer records.

There is however an internal answer record with that information.

 

Indirectly, you could tell from the delay numbers in our datasheet:

screenshot_002.jpg

As you can see (1), for hold, even for the slowest speedgrade, the fastest process is used for characterization. This is because indeed the slowest speedgrade devices could actually be the fastest process.

 

The reason why we do this is simple: it would not be economical to build up a stock-pile of higher/highest speedgrade devices, just in case we would get an order in the future. We manufacture to fulfill demand. Typically, the slowest speedgrades are the cheapest and the best selling. Higher speedgrades are less frequent and therefor more expensive to reduce the demand.

 

In addition, if you don't take my word, here are a few other threads with the same question:

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex5-speedgrade-questions/m-p/68934

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex-5-Speed-Grades/m-p/158502

 

 

Best regards

Dries

 

--------------------------------------------------------------------------------------------------------------------
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jlarin
Adventurer
Adventurer
13,982 Views
Registered: ‎06-07-2012

@driesd wrote:

Hi Jf,

 

I thought you accepted the word of Xilinx employee as proof and documentation? ;)

 

as far as I know, we don't make this direct statement anywhere in our documentation or an (external) answer records.

There is however an internal answer record with that information.

 

 



Hi Dries,

 

Yes I accept the word of Xilinx Employee as proof.  However, it is the fourth item in the list, the first 3 are prefered (easier to forward to co-worker) in the order listed.  Still, especially with your last message referencing the datasheet, I consider myself satisfied (and Accepted as solution your last post).

 

I guess somebody from Xilinx forwarded me that internal answer record a long time ago.

 

Thank you for your help,

 

jf

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