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eng_man
Explorer
Explorer
8,829 Views
Registered: ‎12-22-2010

What maximum frequency will mean here??

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Hi 

I implement this system

	 
	 Port ( 
			  clk,clks,rest  in  STD_LOGIC;			  
			           lo   : out  STD_LOGIC;
	end main;
         
       begin
        process(clk,.........)
        process(clks,........)
        process(synchronization signal)

   end

 the synthesizer report give me the following


Timing Summary:
---------------
Speed Grade: -4

Minimum period: 25.668ns (Maximum Frequency: 38.959MHz)
Minimum input arrival time before clock: 4.297ns
Maximum output required time after clock: 4.283ns

----------------------------------------------------------------------------------------------

Timing constraint: Default period analysis for Clock 'clk'
Clock period: 25.668ns (frequency: 38.959MHz)
Total number of paths / destination ports: 132221536213 / 1277

--------------------------------------------------------------------------------------------

Timing constraint: Default period analysis for Clock 'clks'
Clock period: 4.142ns (frequency: 241.429MHz)
Total number of paths / destination ports: 525 / 70

-----------------------------------------------------------------------------------------------

 

can any one explain what maximum freq here mean???

i think their is no meaning du to that maximum clk freq 38MHZ

and maximum for clks 241MHZ
i am really confuse

can any help what these reprot meaning exactlly

 

---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
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1 Solution

Accepted Solutions
austin
Scholar
Scholar
13,011 Views
Registered: ‎02-27-2008

Two clocks,

 

clk and clks


Each has its own maximum frequency

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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8 Replies
austin
Scholar
Scholar
13,012 Views
Registered: ‎02-27-2008

Two clocks,

 

clk and clks


Each has its own maximum frequency

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

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eng_man
Explorer
Explorer
8,819 Views
Registered: ‎12-22-2010
thank you austin
did you know that i have wait you for two day!!
i was fair that you was busy and will not back to the forum soon
your answers always like gifts in holidays
---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
0 Kudos
bassman59
Historian
Historian
8,801 Views
Registered: ‎02-25-2008

@eng_man wrote:
thank you austin
did you know that i have wait you for two day!!
i was fair that you was busy and will not back to the forum soon
your answers always like gifts in holidays

"Wait for two day?"

Austin posted his (correct) answer two hours and forty minutes after you posted your question!

----------------------------Yes, I do this for a living.
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austin
Scholar
Scholar
8,795 Views
Registered: ‎02-27-2008

b,

 

That might have been his second post.  I think I read it on Friday, and thought I'd give someone else a chance to reply (as the answer was in the question).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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eng_man
Explorer
Explorer
8,787 Views
Registered: ‎12-22-2010

@bassman59 wrote:

@eng_man wrote:
thank you austin
did you know that i have wait you for two day!!
i was fair that you was busy and will not back to the forum soon
your answers always like gifts in holidays

"Wait for two day?"

Austin posted his (correct) answer two hours and forty minutes after you posted your question!


I DID NOT MEAN FOR THIS POST that i wait him

---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
0 Kudos
eng_man
Explorer
Explorer
8,786 Views
Registered: ‎12-22-2010

@austin wrote:

b,

 

That might have been his second post.  I think I read it on Friday, and thought I'd give someone else a chance to reply (as the answer was in the question).

 

 


yes austin

thank , 

---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
0 Kudos
ywu
Xilinx Employee
Xilinx Employee
8,728 Views
Registered: ‎11-28-2007

Check http://myfpgablog.blogspot.com/2010/11/understand-maximum-frequency-reporting.html to see if it helps.

 


@eng_man wrote:

Hi 

I implement this system

	 
	 Port ( 
			  clk,clks,rest  in  STD_LOGIC;			  
			           lo   : out  STD_LOGIC;
	end main;
         
       begin
        process(clk,.........)
        process(clks,........)
        process(synchronization signal)

   end

 the synthesizer report give me the following


Timing Summary:
---------------
Speed Grade: -4

Minimum period: 25.668ns (Maximum Frequency: 38.959MHz)
Minimum input arrival time before clock: 4.297ns
Maximum output required time after clock: 4.283ns

----------------------------------------------------------------------------------------------

Timing constraint: Default period analysis for Clock 'clk'
Clock period: 25.668ns (frequency: 38.959MHz)
Total number of paths / destination ports: 132221536213 / 1277

--------------------------------------------------------------------------------------------

Timing constraint: Default period analysis for Clock 'clks'
Clock period: 4.142ns (frequency: 241.429MHz)
Total number of paths / destination ports: 525 / 70

-----------------------------------------------------------------------------------------------

 

can any one explain what maximum freq here mean???

i think their is no meaning du to that maximum clk freq 38MHZ

and maximum for clks 241MHZ
i am really confuse

can any help what these reprot meaning exactlly

 




Cheers,
Jim
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eng_man
Explorer
Explorer
8,726 Views
Registered: ‎12-22-2010

 


@ywu wrote:

Check http://myfpgablog.blogspot.com/2010/11/understand-maximum-frequency-reporting.html to see if it helps.

 


@eng_man wrote:

Hi 

I implement this system

	 
	 Port ( 
			  clk,clks,rest  in  STD_LOGIC;			  
			           lo   : out  STD_LOGIC;
	end main;
         
       begin
        process(clk,.........)
        process(clks,........)
        process(synchronization signal)

   end

 the synthesizer report give me the following


Timing Summary:
---------------
Speed Grade: -4

Minimum period: 25.668ns (Maximum Frequency: 38.959MHz)
Minimum input arrival time before clock: 4.297ns
Maximum output required time after clock: 4.283ns

----------------------------------------------------------------------------------------------

Timing constraint: Default period analysis for Clock 'clk'
Clock period: 25.668ns (frequency: 38.959MHz)
Total number of paths / destination ports: 132221536213 / 1277

--------------------------------------------------------------------------------------------

Timing constraint: Default period analysis for Clock 'clks'
Clock period: 4.142ns (frequency: 241.429MHz)
Total number of paths / destination ports: 525 / 70

-----------------------------------------------------------------------------------------------

 

can any one explain what maximum freq here mean???

i think their is no meaning du to that maximum clk freq 38MHZ

and maximum for clks 241MHZ
i am really confuse

can any help what these reprot meaning exactlly

 




thank you 

 

---------------------------------------------------------------------------------------------
I am tired of the traditions of peoples --
All I want is to live freely with the girl which I love --
But this is impossible because the traditions of the people stronger than me.
----------------------------------------------------------------------------------------------
0 Kudos