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Registered: ‎04-28-2013

What's happened about the abnormal timing ?

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Hi ,

I 'm looking for some help.

I can't understand why so great timing violation happened?

 

 

 

 

 

Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date              : Sat Nov 26 15:59:19 2016
| Host              : redhatqq running 64-bit CentOS release 6.4 (Final)
| Command           : report_timing -from mmcm_clkout1 -setup -hold -max_paths 2000 -file X19.sdc
| Design            : xxxx
| Device            : xcvu440-flga2892
| Speed File        : -1  PRODUCTION 1.25 10-30-2017
| Temperature Grade : C
--------------------------------------------------------------------------------------------------

Timing Report

Slack (VIOLATED) :        -63.404ns  (required time - arrival time)
  Source:                 U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/ADDR_X_W_reg[22]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout1  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_1_reg[22]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout1  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             mmcm_clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (mmcm_clkout1 rise@12.000ns - mmcm_clkout1 rise@0.000ns)
  Data Path Delay:        75.250ns  (logic 0.906ns (1.204%)  route 74.344ns (98.796%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.381ns = ( 11.381 - 6.000 )
    Source Clock Delay      (SCD):    5.642ns
    Clock Pessimism Removal (CPR):    0.106ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.497ns (routing 1.518ns, distribution 1.979ns)
  Clock Net Delay (Destination): 3.086ns (routing 1.386ns, distribution 1.700ns)
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout1 rise edge)
                                                      0.000     0.000 r  
    AG47                                              0.000     0.000 r  c0_sys_clk_p (IN)
                         net (fo=0)                   0.000     0.000    XILINX_CLK_REF_I_IBUFGDS_inst/I
    HPIOBDIFFINBUF_X0Y133
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.586     0.586 r  XILINX_CLK_REF_I_IBUFGDS_inst/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.104     0.690    XILINX_CLK_REF_I_IBUFGDS_inst/OUT
    AG47                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.690 r  XILINX_CLK_REF_I_IBUFGDS_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.075     1.765    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y5      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1)
                                                     -0.222     1.543 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.501     2.044    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clkout1
    BUFGCE_X0Y121        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.101     2.145 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/u_bufg_addn_ui_clk_1/O
    X2Y7 (CLOCK_ROOT)    net (fo=11912, routed)       3.497     5.642    U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/addn_ui_clkout1
    SLICE_X156Y507       FDCE                                         r  U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/ADDR_X_W_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X156Y507       FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.139     5.781 r  U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/ADDR_X_W_reg[22]/Q
                         net (fo=3, routed)          12.456    18.237    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_reg[25]_1[22]
    SLICE_X161Y505       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.237    18.474 f  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_11/O
                         net (fo=1, routed)          11.842    30.316    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[22]_3
    SLICE_X161Y505       LUT6 (Prop_A6LUT_SLICEL_I5_O)
                                                      0.146    30.462 r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_12/O
                         net (fo=1, routed)          12.274    42.736    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[22]_2
    SLICE_X161Y505       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.147    42.883 f  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_13/O
                         net (fo=1, routed)          12.067    54.950    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[22]_1
    SLICE_X161Y504       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.147    55.097 r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_14/O
                         net (fo=1, routed)          12.209    67.306    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[22]
    SLICE_X161Y504       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.090    67.396 r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_15/O
                         net (fo=2, routed)          13.496    80.892    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_NS[22]
    SLICE_X142Y502       FDCE                                         r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_1_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout1 rise edge)
                                                     12.000    12.000 r  
    AG47                                              0.000    12.000 r  c0_sys_clk_p (IN)
                         net (fo=0)                   0.000    12.000    XILINX_CLK_REF_I_IBUFGDS_inst/I
    HPIOBDIFFINBUF_X0Y133
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.404    12.404 r  XILINX_CLK_REF_I_IBUFGDS_inst/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.055    12.459    XILINX_CLK_REF_I_IBUFGDS_inst/OUT
    AG47                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000    12.459 r  XILINX_CLK_REF_I_IBUFGDS_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.973    13.432    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y5      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1)
                                                      0.350    13.782 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.422    14.204    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clkout1
    BUFGCE_X0Y121        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.091    14.295 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/u_bufg_addn_ui_clk_1/O
    X2Y7 (CLOCK_ROOT)    net (fo=11912, routed)       3.086    17.381    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/addn_ui_clkout1
    SLICE_X142Y502       FDCE                                         r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_1_reg[22]/C
                         clock pessimism              0.106    17.487    
                         clock uncertainty           -0.062    17.425    
    SLICE_X142Y502       FDCE (Setup_CFF_SLICEL_C_D)
                                                      0.063    17.488    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_1_reg[22]
  -------------------------------------------------------------------
                         required time                         17.488    
                         arrival time                         -80.892    
  -------------------------------------------------------------------
                         slack                                -63.404    

Slack (VIOLATED) :        -63.310ns  (required time - arrival time)
  Source:                 U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/ADDR_X_W_reg[22]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout1  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_0_reg[22]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout1  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             mmcm_clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (mmcm_clkout1 rise@12.000ns - mmcm_clkout1 rise@0.000ns)
  Data Path Delay:        75.159ns  (logic 0.906ns (1.205%)  route 74.253ns (98.795%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.381ns = ( 11.381 - 6.000 )
    Source Clock Delay      (SCD):    5.642ns
    Clock Pessimism Removal (CPR):    0.106ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.497ns (routing 1.518ns, distribution 1.979ns)
  Clock Net Delay (Destination): 3.086ns (routing 1.386ns, distribution 1.700ns)
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout1 rise edge)
                                                      0.000     0.000 r  
    AG47                                              0.000     0.000 r  c0_sys_clk_p (IN)
                         net (fo=0)                   0.000     0.000    XILINX_CLK_REF_I_IBUFGDS_inst/I
    HPIOBDIFFINBUF_X0Y133
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.586     0.586 r  XILINX_CLK_REF_I_IBUFGDS_inst/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.104     0.690    XILINX_CLK_REF_I_IBUFGDS_inst/OUT
    AG47                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.690 r  XILINX_CLK_REF_I_IBUFGDS_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.075     1.765    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y5      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1)
                                                     -0.222     1.543 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.501     2.044    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clkout1
    BUFGCE_X0Y121        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.101     2.145 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/u_bufg_addn_ui_clk_1/O
    X2Y7 (CLOCK_ROOT)    net (fo=11912, routed)       3.497     5.642    U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/addn_ui_clkout1
    SLICE_X156Y507       FDCE                                         r  U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/ADDR_X_W_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X156Y507       FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.139     5.781 r  U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/ADDR_X_W_reg[22]/Q
                         net (fo=3, routed)          12.456    18.237    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_reg[25]_1[22]
    SLICE_X161Y505       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.237    18.474 f  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_11/O
                         net (fo=1, routed)          11.842    30.316    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[22]_3
    SLICE_X161Y505       LUT6 (Prop_A6LUT_SLICEL_I5_O)
                                                      0.146    30.462 r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_12/O
                         net (fo=1, routed)          12.274    42.736    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[22]_2
    SLICE_X161Y505       LUT5 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.147    42.883 f  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_13/O
                         net (fo=1, routed)          12.067    54.950    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[22]_1
    SLICE_X161Y504       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.147    55.097 r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_14/O
                         net (fo=1, routed)          12.209    67.306    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[22]
    SLICE_X161Y504       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.090    67.396 r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[22]_i_1_15/O
                         net (fo=2, routed)          13.405    80.801    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_NS[22]
    SLICE_X142Y502       FDCE                                         r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_0_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout1 rise edge)
                                                     12.000    12.000 r  
    AG47                                              0.000    12.000 r  c0_sys_clk_p (IN)
                         net (fo=0)                   0.000    12.000    XILINX_CLK_REF_I_IBUFGDS_inst/I
    HPIOBDIFFINBUF_X0Y133
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.404    12.404 r  XILINX_CLK_REF_I_IBUFGDS_inst/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.055    12.459    XILINX_CLK_REF_I_IBUFGDS_inst/OUT
    AG47                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000    12.459 r  XILINX_CLK_REF_I_IBUFGDS_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.973    13.432    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y5      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1)
                                                      0.350    13.782 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.422    14.204    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clkout1
    BUFGCE_X0Y121        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.091    14.295 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/u_bufg_addn_ui_clk_1/O
    X2Y7 (CLOCK_ROOT)    net (fo=11912, routed)       3.086    17.381    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/addn_ui_clkout1
    SLICE_X142Y502       FDCE                                         r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_0_reg[22]/C
                         clock pessimism              0.106    17.487    
                         clock uncertainty           -0.062    17.425    
    SLICE_X142Y502       FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.066    17.491    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_0_reg[22]
  -------------------------------------------------------------------
                         required time                         17.491    
                         arrival time                         -80.801    
  -------------------------------------------------------------------
                         slack                                -63.310    

Slack (VIOLATED) :        -61.465ns  (required time - arrival time)
  Source:                 U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/ADDR_X_W_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout1  {rise@0.000ns fall@3.000ns period=6.000ns})
  Destination:            U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_1_reg[12]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout1  {rise@0.000ns fall@3.000ns period=6.000ns})
  Path Group:             mmcm_clkout1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (mmcm_clkout1 rise@12.000ns - mmcm_clkout1 rise@0.000ns)
  Data Path Delay:        73.283ns  (logic 0.491ns (0.670%)  route 72.792ns (99.330%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        -0.184ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.367ns = ( 11.367 - 6.000 )
    Source Clock Delay      (SCD):    5.656ns
    Clock Pessimism Removal (CPR):    0.106ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.101ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.511ns (routing 1.518ns, distribution 1.993ns)
  Clock Net Delay (Destination): 3.072ns (routing 1.386ns, distribution 1.686ns)
  Timing Exception:       MultiCycle Path   Setup -end   2    

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout1 rise edge)
                                                      0.000     0.000 r  
    AG47                                              0.000     0.000 r  c0_sys_clk_p (IN)
                         net (fo=0)                   0.000     0.000    XILINX_CLK_REF_I_IBUFGDS_inst/I
    HPIOBDIFFINBUF_X0Y133
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.586     0.586 r  XILINX_CLK_REF_I_IBUFGDS_inst/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.104     0.690    XILINX_CLK_REF_I_IBUFGDS_inst/OUT
    AG47                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000     0.690 r  XILINX_CLK_REF_I_IBUFGDS_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           1.075     1.765    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y5      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1)
                                                     -0.222     1.543 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.501     2.044    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clkout1
    BUFGCE_X0Y121        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.101     2.145 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/u_bufg_addn_ui_clk_1/O
    X2Y7 (CLOCK_ROOT)    net (fo=11912, routed)       3.511     5.656    U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/addn_ui_clkout1
    SLICE_X158Y509       FDCE                                         r  U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/ADDR_X_W_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X158Y509       FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.139     5.795 r  U_dcore/U_mpeg_core/U_vcom/U_pa_write_0/ADDR_X_W_reg[12]/Q
                         net (fo=3, routed)          12.393    18.188    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_reg[25]_1[12]
    SLICE_X167Y508       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146    18.334 f  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[12]_i_1_12/O
                         net (fo=1, routed)          11.693    30.027    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[12]_3
    SLICE_X166Y508       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.051    30.078 r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[12]_i_1_13/O
                         net (fo=1, routed)          11.635    41.713    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[12]_2
    SLICE_X166Y508       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.051    41.764 f  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[12]_i_1_14/O
                         net (fo=1, routed)          11.914    53.678    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[12]_1
    SLICE_X167Y508       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.051    53.729 r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[12]_i_1_15/O
                         net (fo=1, routed)          11.794    65.523    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_ADDR_X_W_NS[12]
    SLICE_X164Y508       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.053    65.576 r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/xlnx_opt_LUT_ADDR_X_W_CS_0[12]_i_1_16/O
                         net (fo=2, routed)          13.363    78.939    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_NS[12]
    SLICE_X142Y500       FDCE                                         r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_1_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout1 rise edge)
                                                     12.000    12.000 r  
    AG47                                              0.000    12.000 r  c0_sys_clk_p (IN)
                         net (fo=0)                   0.000    12.000    XILINX_CLK_REF_I_IBUFGDS_inst/I
    HPIOBDIFFINBUF_X0Y133
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.404    12.404 r  XILINX_CLK_REF_I_IBUFGDS_inst/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.055    12.459    XILINX_CLK_REF_I_IBUFGDS_inst/OUT
    AG47                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_I_O)
                                                      0.000    12.459 r  XILINX_CLK_REF_I_IBUFGDS_inst/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.973    13.432    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clk_in
    MMCME3_ADV_X0Y5      MMCME3_ADV (Prop_MMCME3_ADV_CLKIN1_CLKOUT1)
                                                      0.350    13.782 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT1
                         net (fo=1, routed)           0.422    14.204    U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/mmcm_clkout1
    BUFGCE_X0Y121        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.091    14.295 r  U_VU440_ONLYPHY/inst/u_ddr3_infrastructure/u_bufg_addn_ui_clk_1/O
    X2Y7 (CLOCK_ROOT)    net (fo=11912, routed)       3.072    17.367    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/addn_ui_clkout1
    SLICE_X142Y500       FDCE                                         r  U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_1_reg[12]/C
                         clock pessimism              0.106    17.473    
                         clock uncertainty           -0.062    17.411    
    SLICE_X142Y500       FDCE (Setup_DFF_SLICEL_C_D)
                                                      0.063    17.474    U_dcore/U_mpeg_core/U_EMI_IntBus/U_BUS_WCTRL/ADDR_X_W_CS_1_reg[12]
  -------------------------------------------------------------------
                         required time                         17.474    
                         arrival time                         -78.939    
  -------------------------------------------------------------------
                         slack                                -61.465    

nonsense
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Highlighted
Guide
Guide
1,122 Views
Registered: ‎01-23-2009

Re: What's happened about the abnormal timing ?

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Wow! Those are pretty impressive route times!

 

I have never seen times like that - something is GROSSLY wrong here.

 

Looking at the placement, these cells are not all that far apart - I doubt a pblock is going to help (in fact, I have never seen pblocks really help timing in Vivado - the placer does a pretty good job on its own).

 

However, these route times are IMMENSE! The only two explanations I might give is

  - this area of the FPGA is massively congested, and the routes are going all over the place to try and get through the congested area

     - you should be able to see this by looking at the Device View, and selecting the Routing Resources option. You can then select one of these nets (directly from the timing report) to highlight it. If there is a congestion problem, you will see the route go in a huge circuitous path between the source and the destination (which are actually relatively close together)

     - you can also look at the congestion map in the device view by right clicking in an empty area and selecting "Metric -> <each of the congestion metrics>"

  - there is some incorrect constraint making the tools think there is a hold time it needs to fix

      - this is unlikely since the source and destination flip-flop are on the same domain. You can see this by looking at the hold time report for this path, which can be done with

        report_timing -from [get_cells <source_ff>] -to [get_cells <destination_ff>] -hold

      - the requirement on the path should be 0; if it is anything else then there is a constraint problem

 

If it is neither of these two (or if the route doesn't look bad), then there may be something wrong with the tool. These numbers are suspiciously incorrect (like more than 10x what they should be)...

 

Avrum

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3 Replies
Highlighted
Moderator
Moderator
853 Views
Registered: ‎03-16-2017

Re: What's happened about the abnormal timing ?

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Hi @liubo_fpga,

 

Going through the timing report , the one thing i have observed is high routing delay 98.7%  which needs to be reduced. 

Which has been led by high net delays in data path as shown below.

 

Apply pblocks on slices shown below and do proper floor planning to reduce these net delays.

 

ooCapture.JPG

 

Regards,

hemangd

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
0 Kudos
Highlighted
Guide
Guide
1,123 Views
Registered: ‎01-23-2009

Re: What's happened about the abnormal timing ?

Jump to solution

Wow! Those are pretty impressive route times!

 

I have never seen times like that - something is GROSSLY wrong here.

 

Looking at the placement, these cells are not all that far apart - I doubt a pblock is going to help (in fact, I have never seen pblocks really help timing in Vivado - the placer does a pretty good job on its own).

 

However, these route times are IMMENSE! The only two explanations I might give is

  - this area of the FPGA is massively congested, and the routes are going all over the place to try and get through the congested area

     - you should be able to see this by looking at the Device View, and selecting the Routing Resources option. You can then select one of these nets (directly from the timing report) to highlight it. If there is a congestion problem, you will see the route go in a huge circuitous path between the source and the destination (which are actually relatively close together)

     - you can also look at the congestion map in the device view by right clicking in an empty area and selecting "Metric -> <each of the congestion metrics>"

  - there is some incorrect constraint making the tools think there is a hold time it needs to fix

      - this is unlikely since the source and destination flip-flop are on the same domain. You can see this by looking at the hold time report for this path, which can be done with

        report_timing -from [get_cells <source_ff>] -to [get_cells <destination_ff>] -hold

      - the requirement on the path should be 0; if it is anything else then there is a constraint problem

 

If it is neither of these two (or if the route doesn't look bad), then there may be something wrong with the tool. These numbers are suspiciously incorrect (like more than 10x what they should be)...

 

Avrum

View solution in original post

Highlighted
Explorer
Explorer
814 Views
Registered: ‎04-28-2013

Re: What's happened about the abnormal timing ?

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Hi ,

Thanks for your reply.

I checked my constraint file with your remind of "incorrect constraint" and find an error as belows !

 

set_multicycle_path -setup -end -from [...] -to  [get_cells {...ADDR_X_W_CS_?_reg[*]}] 2

set_multicycle_path -hold  -end -from [...] -to  [get_cells {...ADDR_X_W_CS_?_reg}]      1

 

The correct should be as belows

set_multicycle_path -setup -end -from [...] -to  [get_cells {...ADDR_X_W_CS_?_reg[*]}] 2

set_multicycle_path -hold  -end -from [...] -to  [get_cells {...ADDR_X_W_CS_?_reg[*]}]  1

 

Thanks a lot !

 

 

nonsense
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