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Visitor tip.can19
Visitor
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Registered: ‎10-23-2018

What would be difference between clock latency and propagation delay?

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I believe the clock latency is the total time it takes from the clock source to an end point.

 

latency.png


Whereas, the propagation delay would simply be the delay between the two edges, like an input output example below.

 

propagation.png


So in other words, does this mean propagation delay between clock signals is kind of a clock skew, which is measure of latency if one clock period capture?

 

thanks

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310 Views
Registered: ‎01-22-2015

Re: What would be difference between clock latency and propagation delay?

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@tip.can19

 

Welcome to the Xilinx Forum!

 

Inside Xilinx FPGAs you will typically find that a clock is generated by a clock management tile (eg. MMCM or PLL) and distributed throughout the FPGA via a clock tree. The clock tree is composed of clock buffers and special clock routing paths. As the clock signal moves through the clock tree, it experiences the propagation delay associated with the buffers and paths. At a particular point in the clock tree, we define clock latency as the sum of the propagation delays experienced by the clock.

 

Since the clock tree has many branches, you will find that the clock reaches many points of the clock tree. For any two points in the clock tree, you will find that the clock has different latency. This difference in latency is called clock skew.

 

The word “latency” comes up elsewhere in FPGA lingo. For example, there is the calculation latency associated with some Xilinx IP (eg. Divider Generator). Calculation latency is a time-measurement in clock-cycles between when the calculation starts and when the calculation result becomes available.

 

Cheers,

Mark

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Re: What would be difference between clock latency and propagation delay?

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Moderator
Moderator
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Registered: ‎05-31-2017

Re: What would be difference between clock latency and propagation delay?

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Hi @tip.can19,

 

Propogation delay is the time taken for a signal to propagate through a gate or net. 

Clock latency is the delay between the clock source pin and the flipflop clock pin in other words clock latency is the number of clock pulses required to give the first output.

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Highlighted
311 Views
Registered: ‎01-22-2015

Re: What would be difference between clock latency and propagation delay?

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@tip.can19

 

Welcome to the Xilinx Forum!

 

Inside Xilinx FPGAs you will typically find that a clock is generated by a clock management tile (eg. MMCM or PLL) and distributed throughout the FPGA via a clock tree. The clock tree is composed of clock buffers and special clock routing paths. As the clock signal moves through the clock tree, it experiences the propagation delay associated with the buffers and paths. At a particular point in the clock tree, we define clock latency as the sum of the propagation delays experienced by the clock.

 

Since the clock tree has many branches, you will find that the clock reaches many points of the clock tree. For any two points in the clock tree, you will find that the clock has different latency. This difference in latency is called clock skew.

 

The word “latency” comes up elsewhere in FPGA lingo. For example, there is the calculation latency associated with some Xilinx IP (eg. Divider Generator). Calculation latency is a time-measurement in clock-cycles between when the calculation starts and when the calculation result becomes available.

 

Cheers,

Mark

Visitor tip.can19
Visitor
300 Views
Registered: ‎10-23-2018

Re: What would be difference between clock latency and propagation delay?

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Thanks markg@prosensing.com for the detailed answer and explanation

 

Thanks all.

Regards

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