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6,359 Views
Registered: ‎02-18-2009

Where do I look for " Maximum frequency" of operation.

Hi,

 

I am using Xilinx  ISE 9.2i. I am still in the learning phase, and according to a tutorial I have for the 7.1i, If I click on, "Post Place & Route Static Timing Report " under " Place and Route", I can view the maximum frequency of operation. 

 

But, unfortunatly I am not able to find out how to look for it, as the report generated just speaks about the" Maximum period".

 

I am sorry, if any key details were missing in my question. Please help me. I am attaching a screenshot and the log file. Hope it helps you to understand my question.

 

Thank you,

 

Best regards,

Sandeepsarma 

 

PS: If this question is posted at the wrong place please shoot an email to - ssj@temple.edu 

 

----------------------------------------------------------------------------------------------------------------------------------------------------------------

log file

 

--------------------------------------------------------------------------------
Release 9.2i - Timing Analyzer J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Design file:              D:\Xilinx_Attempt4\Attempt_Thursday\seq_ckts.ncd
Physical constraint file: D:\Xilinx_Attempt4\Attempt_Thursday\seq_ckts.pcf
Device,speed:             xcv100e,-8 (PRODUCTION 1.70 2007-04-13)
Report level:             verbose report

Environment Variable      Effect
--------------------      ------
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
   a 50 Ohm transmission line loading model.  For the details of this model,
   and for more information on accounting for different loading conditions,
   please see the device datasheet.

================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 10 ns HIGH 50%;

 714 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   6.116ns.
--------------------------------------------------------------------------------
Slack:                  3.884ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cnt_reg[7] (FF)
  Destination:          cnt_reg[7] (FF)
  Requirement:          10.000ns
  Data Path Delay:      6.116ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         clk_c rising at 0.000ns
  Destination Clock:    clk_c rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Data Path: cnt_reg[7] to cnt_reg[7]
    Delay type         Delay(ns)  Logical Resource(s)
    ----------------------------  -------------------
    Tcko                  0.772   cnt_reg[7]
    net (fanout=3)        0.880   cnt_reg_c[7]
    Tilo                  0.398   res_cnt_3
    net (fanout=1)        0.697   res_cnt_3
    Tilo                  0.398   res_cnt
    net (fanout=10)       1.439   cnt_reg
    Topfcky               1.532   cnt_reg_qxu[6]
                                  cnt_reg_cry[6]
                                  cnt_reg_s[7]
                                  cnt_reg[7]
    ----------------------------  ---------------------------
    Total                 6.116ns (3.100ns logic, 3.016ns route)
                                  (50.7% logic, 49.3% route)

--------------------------------------------------------------------------------
Slack:                  3.898ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cnt_reg[7] (FF)
  Destination:          cnt_reg[6] (FF)
  Requirement:          10.000ns
  Data Path Delay:      6.102ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         clk_c rising at 0.000ns
  Destination Clock:    clk_c rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Data Path: cnt_reg[7] to cnt_reg[6]
    Delay type         Delay(ns)  Logical Resource(s)
    ----------------------------  -------------------
    Tcko                  0.772   cnt_reg[7]
    net (fanout=3)        0.880   cnt_reg_c[7]
    Tilo                  0.398   res_cnt_3
    net (fanout=1)        0.697   res_cnt_3
    Tilo                  0.398   res_cnt
    net (fanout=10)       0.611   cnt_reg
    Tilo                  0.398   A_ibuf_RNIRQI4
    net (fanout=4)        1.400   A_ibuf_RNIRQI4
    Tceck                 0.548   cnt_reg[6]
    ----------------------------  ---------------------------
    Total                 6.102ns (2.514ns logic, 3.588ns route)
                                  (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------
Slack:                  3.898ns (requirement - (data path - clock path skew + uncertainty))
  Source:               cnt_reg[7] (FF)
  Destination:          cnt_reg[7] (FF)
  Requirement:          10.000ns
  Data Path Delay:      6.102ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         clk_c rising at 0.000ns
  Destination Clock:    clk_c rising at 10.000ns
  Clock Uncertainty:    0.000ns

  Data Path: cnt_reg[7] to cnt_reg[7]
    Delay type         Delay(ns)  Logical Resource(s)
    ----------------------------  -------------------
    Tcko                  0.772   cnt_reg[7]
    net (fanout=3)        0.880   cnt_reg_c[7]
    Tilo                  0.398   res_cnt_3
    net (fanout=1)        0.697   res_cnt_3
    Tilo                  0.398   res_cnt
    net (fanout=10)       0.611   cnt_reg
    Tilo                  0.398   A_ibuf_RNIRQI4
    net (fanout=4)        1.400   A_ibuf_RNIRQI4
    Tceck                 0.548   cnt_reg[7]
    ----------------------------  ---------------------------
    Total                 6.102ns (2.514ns logic, 3.588ns route)
                                  (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.116|         |         |         |
---------------+---------+---------+---------+---------+


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 714 paths, 0 nets, and 220 connections


Analysis completed Thu Feb 19 15:20:27 2009
--------------------------------------------------------------------------------

Timing Analyzer Settings:
-------------------------
OpenPCF D:\Xilinx_Attempt4\Attempt_Thursday\seq_ckts.pcf
Speed -8
IncludeNets
ExcludeNets
SelectFailingTimingConstraint False
IncludeNoTimingConstraint False
Report normal
MaxPathsPerTimingConstraint 3
ReportFastestPaths False
GenerateDataSheet True
GenerateTimeGroup False
DefineEndpoints ToAll
DefineEndpoints FromAll
OmitUserConstraints False
DropTimingConstraint
SetForce Off
ProratingOptions 

Peak Memory Usage: 93 MB
 

capture_19022009_154206.jpg
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1 Reply
6,344 Views
Registered: ‎02-18-2009

Re: Where do I look for " Maximum frequency" of operation.

since F =1/T

 

should i consider this 

?

 

 

All values displayed in nanoseconds (ns)

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.116|         |         |         |

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