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Explorer
Explorer
10,506 Views
Registered: ‎09-28-2012

Why does the clk enable delay parameter is so large?

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Hi,

 

I work around Timing Analyzer with a VHDL project. I find that the report has a large clk_enable timing delay parameter (5.752(R)), see below please. On Virtex 4 datasheet, I see that CLB has a much smaller TCECK, which is only about

 

0.58-0.16     0.57-0.16     0.64-0.16    0.75-0.16             ns, Min

 

on page 31/58 of ds302.pdf. Can anybody explain what clk_enable (5.752(R)) is to me?

 

 

Thanks,

 

 

 

 

 

 

Release 9.2.04i - Timing Analyzer J.40

Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.

Physical constraint file: C:\Xilinx92i\exam\DUT.pcf

Device,speed: xc4vlx100,-12 (PRODUCTION 1.68 2007-11-08, STEPPING level 1)

Report level: error report

 

 

 

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to clock clk

------------+------------+------------+------------------+--------+

| Setup to | Hold to | | Clock |

Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |

------------+------------+------------+------------------+--------+

clk_enable | 5.752(R)| 0.126(R)|clk_BUFGP | 0.000|

dIn_im<0> | -0.129(R)| 2.203(R)|clk_BUFGP | 0.000|

dIn_im<1> | -0.238(R)| 1.779(R)|clk_BUFGP | 0.000|

dIn_im<2> | -0.342(R)| 2.105(R)|clk_BUFGP | 0.000|

 

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Explorer
Explorer
17,860 Views
Registered: ‎09-28-2012

Re: Why does the clk enable delay parameter is so large?

Jump to solution

Hi,

 

In order to solve the previous problem, I create a simple DFF project. This time the clk enable signal has negative delay parameter: -1.822 nS, see below please. 

 

This puzzles me even more to previous question. The dalay time changes from positive to negative. It still does not match the data sheet Tceck. Could you exolain it to me?

 


Thanks,

 

 

 

 

 

 

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
din | 1.714(R)| 0.070(R)|clk_BUFGP | 0.000|
ena | -1.822(R)| 2.732(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+

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3 Replies
Highlighted
Explorer
Explorer
17,861 Views
Registered: ‎09-28-2012

Re: Why does the clk enable delay parameter is so large?

Jump to solution

Hi,

 

In order to solve the previous problem, I create a simple DFF project. This time the clk enable signal has negative delay parameter: -1.822 nS, see below please. 

 

This puzzles me even more to previous question. The dalay time changes from positive to negative. It still does not match the data sheet Tceck. Could you exolain it to me?

 


Thanks,

 

 

 

 

 

 

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
din | 1.714(R)| 0.070(R)|clk_BUFGP | 0.000|
ena | -1.822(R)| 2.732(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+

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Historian
Historian
10,478 Views
Registered: ‎02-25-2008

Re: Why does the clk enable delay parameter is so large?

Jump to solution

@robertwilliam wrote:

Hi,

 

I work around Timing Analyzer with a VHDL project. I find that the report has a large clk_enable timing delay parameter (5.752(R)), see below please. On Virtex 4 datasheet, I see that CLB has a much smaller TCECK, which is only about

 

0.58-0.16     0.57-0.16     0.64-0.16    0.75-0.16             ns, Min

 

on page 31/58 of ds302.pdf. Can anybody explain what clk_enable (5.752(R)) is to me?

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to clock clk

------------+------------+------------+------------------+--------+

| Setup to | Hold to | | Clock |

Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |

------------+------------+------------+------------------+--------+

clk_enable | 5.752(R)| 0.126(R)|clk_BUFGP | 0.000|

dIn_im<0> | -0.129(R)| 2.203(R)|clk_BUFGP | 0.000|

dIn_im<1> | -0.238(R)| 1.779(R)|clk_BUFGP | 0.000|

dIn_im<2> | -0.342(R)| 2.105(R)|clk_BUFGP | 0.000|

 


The (R) is the relevant clock edge, in this case, rising. The report is telling you that the clk_enable signal has a worst-case setp time requirement of 5.752 ns to the clock signal. You should delve further into the timing report to see which flip-flop requires this setup time.

----------------------------Yes, I do this for a living.
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Historian
Historian
10,477 Views
Registered: ‎02-25-2008

Re: Why does the clk enable delay parameter is so large?

Jump to solution

@robertwilliam wrote:

Hi,

 

In order to solve the previous problem, I create a simple DFF project. This time the clk enable signal has negative delay parameter: -1.822 nS, see below please. 

 

This puzzles me even more to previous question. The dalay time changes from positive to negative. It still does not match the data sheet Tceck. Could you exolain it to me?

 


Thanks,

 

 

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
| Setup to | Hold to | | Clock |
Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
------------+------------+------------+------------------+--------+
din | 1.714(R)| 0.070(R)|clk_BUFGP | 0.000|
ena | -1.822(R)| 2.732(R)|clk_BUFGP | 0.000|
------------+------------+------------+------------------+--------+


Basically, your data and enable paths are different.

 

I'll bet you are taking din and ena into the FPGA and clocking them. Neither signal is forced into an input flip-flop, nor are their timings constrained (using OFFSET IN) and so their paths into the FPGA to the destination flip-flop are whatever the tools want them to be.

 

You need to constrain the inputs, and you should probably ensure that they go into IFFs before use in the fabric.

----------------------------Yes, I do this for a living.
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