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carnby
Explorer
Explorer
12,113 Views
Registered: ‎11-23-2013

Why does the delay differs in setup and hold analysis??

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Hello,

When I check the timing path of my DDR input signal, I found that the delay of the same element differs in different analysis.

 

The following is the destination clock path in "Setup" analysis. We can see that the delay through IBUFDS = 0.382, delay through IDELAYE2 = 0.264, delay through BUFIO = 0.482.

a.png

 

And the next figure shows the delay of the same IBUFDS, IDELAYE2 and BUFIO in "Hold" analysis. We can see that delay  through IBUFDS = 0.758, delay through IDELAYE2 =0.666, delay through BUFIO = 1.140. All the delay become lager than they were in the "Setup" analysis. How does this happen???

b.jpg

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vemulad
Xilinx Employee
Xilinx Employee
19,951 Views
Registered: ‎09-20-2012
Hi,

The difference in delays seen is because of multi corner analysis. The vivado does min/max checks at fast process corner and slow process corners and reports the worst case scenario.

Check the below thread http://forums.xilinx.com/t5/General-Technical-Discussion/What-is-the-mean-of-process-corner/td-p/326871

Thanks,
Deepika.
Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
19,952 Views
Registered: ‎09-20-2012
Hi,

The difference in delays seen is because of multi corner analysis. The vivado does min/max checks at fast process corner and slow process corners and reports the worst case scenario.

Check the below thread http://forums.xilinx.com/t5/General-Technical-Discussion/What-is-the-mean-of-process-corner/td-p/326871

Thanks,
Deepika.
Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

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carnby
Explorer
Explorer
12,090 Views
Registered: ‎11-23-2013

Thank you!

Your answer was short, but very clear.

 

In setup analysis, the max delay data path and the min delay clock path will be analyzed.

In hold analysis, the min delay data path, and the max delay clcok path will be analyzed.

 

 

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avrumw
Guide
Guide
12,086 Views
Registered: ‎01-23-2009

Actually, its more complex than that...

 

In Vivado (by default), setup and hold checks are done at both process corners (which are called "Fast" and "Slow").

 

For the purposes of reporting, the process corner that results in the smallest slack is reported for each check.

 

By extrapolation (since you didn't show us the path summary), It looks like the setup check has less slack at "Fast Process Corner". So, for this check, the maximum delay at Fast process corner [fast_max] is used for the source clock and datapath delay, and the minimum delay at Fast process corner [fast_min] is used for the destination clock delay.

 

Since the tool reported this path, this means that the other setup check - at "Slow Process Corner" had more slack. For this case, the source and datapath delay would be done at [slow_max] and the destination clock delay would be done [slow_min].

 

The other path reported is a hold check - again, I am extrapolating that it is at "Slow Process Corner". So in this case, the source clock and datapath delay are done at [slow_min], and the destination clock delay at [slow_max].

 

The delay number for a given component will be different under all four of these cases ([slow_max],[slow_min],[fast_max], and [fast_min]).

 

Avrum

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carnby
Explorer
Explorer
12,079 Views
Registered: ‎11-23-2013

 thanks!

 

I didn't know timing analysis so much. Thanks for your explanation.

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