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Explorer
Explorer
774 Views
Registered: ‎09-28-2012

Why does this multi-cycle constraint fail?

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Hello,

I learn multicycle timing constraints from a past post:

 

https://forums.xilinx.com/t5/Timing-Analysis/Is-the-multicycle-path-is-valid-for-my-design/td-p/724019

 

I create a design for a multicycle 2 logic as the above link. clock frequency is 100MHz. In fact, the timing closure is closed even without a multicycle constraint. When I add the multicycle=2 timing constraint, the slack is violated as shown in the screen shot:

 

mcyc2a.PNG

 

The project is also attached in this post. What is wrong in the timing file?

 

Thanks,

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1 Solution

Accepted Solutions
Historian
Historian
1,056 Views
Registered: ‎01-23-2009

Re: Why does this multi-cycle constraint fail?

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The  set_multicycle_path command moves both the hold edge and the setup edge forward by the specified amount. In most cases, this leaves the hold check in the wrong place, which is the failure you are seeing.

 

If this is a multicycle path between flip-flops on the same domain then you need a set_multicycle_path -hold <N-1> on the path to fix the hold check.

 

Since your multicycle path is 2 long, you need a

 

set_multicycle_path -hold 1 -from....

 

Avrum

1 Reply
Historian
Historian
1,057 Views
Registered: ‎01-23-2009

Re: Why does this multi-cycle constraint fail?

Jump to solution

The  set_multicycle_path command moves both the hold edge and the setup edge forward by the specified amount. In most cases, this leaves the hold check in the wrong place, which is the failure you are seeing.

 

If this is a multicycle path between flip-flops on the same domain then you need a set_multicycle_path -hold <N-1> on the path to fix the hold check.

 

Since your multicycle path is 2 long, you need a

 

set_multicycle_path -hold 1 -from....

 

Avrum