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Registered: ‎01-26-2021

Why is FCLK_RESET0_N toggling?


I'm pretty new to FPGA programming and have implemented a simple square wave program successfully following the "Blink" pattern of RIT's RavvenLabs.  (link)   That IP produces a 0.5Hz square wave from the 50MHz FCLK_CLK0 signal.

What I did

This has been working well, but this weekend I decided I wanted to be able to export a clock signal from Zynq to another device.   To achieve this I supplemented that working "Blink" design by doing "Create Port" on the FCLK_CLK0 pin in of the Zynq 7010 Processing System in Vivado.   Finally I added a constraint that associated IO_L13P_T2_MRCC_35 with that Port:

### JA1.38 (IO_L13P_T2_MRCC_35)
set_property PACKAGE_PIN H16 [get_ports FCLK_CLK0]
set_property IOSTANDARD LVCMOS33 [get_ports FCLK_CLK0]


What I experienced

Once I loaded this new design from Ubuntu on to the PL, I noticed that although my logic analyzer suggested that the clock was successfully output, the Blink IP that had been working was now producing a 50Mhz square wave instead of a 0.5Hz square wave.   It looks like the cause of that is that the FCLK_RESET0_N that feeds that Blink IP is now toggling at 50Mhz, instead of being steadily inactive.    This causes the Blink IP to reset every cycle of FCLK_CLK0.

My questions

Why would sharing the FCLK_CLK0  cause the FCLK_RESET0_N to toggle like this?

What reading or tooling activity should I do to better understand this?

Are there available any simple designs/tutorials that demonstrate a Zynq exporting a clock signal?


Thank you.

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