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2,053 Views
Registered: ‎04-11-2017

Why is my reset treated as a clock ?

In my design I have a reset port which is connected to reset on fpga board. This is showing up as a clock in timing constraints wizard.

Is there any switch to add exception to such cases ?

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Moderator
Moderator
2,044 Views
Registered: ‎03-16-2017

Hi @anjaneyulu.challa9,

 

Can you show us that reset port through synthesized design? Snapshots will be helpful to understand. And also provide the constraint file which you have applied. 

 

Regards,

hemangd

Regards,
hemangd

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Teacher
Teacher
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Registered: ‎07-09-2009

WHat language / tools you using ?

 

My bet is that the reset signal is used some where in the code as a clock, the tools are quite good at noticing that.

     BTW: that could be a latch you have created with the reset, 

 

Have you looked through the outputs on the terminal window

    particularly the warnings, anything strange, like latches inferred , signals removed that you think should not be ?

 

 

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Xilinx Employee
Xilinx Employee
1,979 Views
Registered: ‎07-16-2008

Please check the reset signal connectivity in implemented design. What is the fanout of the reset? Can it be that a BUFG is inserted?

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1,969 Views
Registered: ‎04-11-2017

@graces fan out is around 3000 and yes a BUFG is inserted

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1,968 Views
Registered: ‎04-11-2017

@drjohnsmith I'm using verilog and vivado. I dont see that reset is used as a clock anywhere in the design. No warnings as such
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1,964 Views
Registered: ‎04-11-2017

Hi @hemangd ,

 

Here is the snap shot of synthesized design and no extra constraints applied other than the pin locs

 

2018-07-05 08_37_56-192.168.24.226_6 (inhyvnc12.inedasystems.com_6 (achalla)) - VNC Viewer.png

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Moderator
Moderator
1,951 Views
Registered: ‎03-16-2017

Hi @anjaneyulu.challa9,

 

And also provide the snapshot of timing constraint wizard where you see this reset as a clock. 

 

Regards,

hemangd

Regards,
hemangd

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Highlighted
1,937 Views
Registered: ‎04-11-2017

Hi @hemangd ,

Sorry I have attached the wrong schematic Please find the attachemnts below 2018-07-05 10_09_28-192.168.24.226_6 (inhyvnc12.inedasystems.com_6 (achalla)) - VNC Viewer.png2018-07-05 10_11_04-192.168.24.226_6 (inhyvnc12.inedasystems.com_6 (achalla)) - VNC Viewer.png

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Xilinx Employee
Xilinx Employee
1,925 Views
Registered: ‎05-14-2008


@anjaneyulu.challa9 wrote:

Hi @hemangd ,

Sorry I have attached the wrong schematic Please find the attachemnts below 2018-07-05 10_09_28-192.168.24.226_6 (inhyvnc12.inedasystems.com_6 (achalla)) - VNC Viewer.png2018-07-05 10_11_04-192.168.24.226_6 (inhyvnc12.inedasystems.com_6 (achalla)) - VNC Viewer.png


In your schematic, select the net right after the BUFG, and then go to "Net Properties -> Connectivity or Cell Pins" to see if this net drives any CLK pins of sequential elements.

 

-vivian

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net_connectivity.png
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Highlighted
1,540 Views
Registered: ‎04-11-2017

No it doesn't drive any clocks
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Xilinx Employee
Xilinx Employee
1,533 Views
Registered: ‎05-14-2008

Does it drive any G pin of latches?

 

-vivian

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Guide
Guide
1,449 Views
Registered: ‎01-23-2009

If the timing constraint wizard is identifying the net as a clock, then it is most likely driving a clock (or gate of a latch) pin somewhere in the design.

 

The tools can help you find it - open the synthesized design and type:

 

show_objects [filter  [all_fanout -flat -endpoints_only [get_ports CPU_RESET]] "IS_CLOCK && IS_LEAF"]

 

Avrum