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Explorer
Explorer
1,481 Views
Registered: ‎09-28-2012

Why is there a no_clock Check Timing warning?

Hi,

I set a clock period (10nS) timing constraint to a small project. In the timing summary, it has a few no_clock High Severity warning, as seen in below picture.

In the schematic, the bold blue line in fact connect to RxBitCount_v_reg[0] clock pin (which is out of screen in the picture). Why does the timing summary insist that no_clock warning? Is there a way to eliminate the warning?

 

 

Thanks,

 

 

 

 

no_clock.PNG

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4 Replies
Moderator
Moderator
1,461 Views
Registered: ‎03-16-2017

Re: Why is there a no_clock Check Timing warning?

Hi @robertwilliam,

 

Can you run "report_clocks" command and provide the report to evaluate? And also provide your xdc constraints file which contains clocking constraints. 

 

 Please make sure that you should always generate a clock either from an MMCM/PLL or using a gated clock buffer (BUFGCE/BUFHCE). 

 

Regards,

hemangd

Regards,
hemangd

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Highlighted
Explorer
Explorer
1,427 Views
Registered: ‎09-28-2012

Re: Why is there a no_clock Check Timing warning?

Thanks mehangd for your reply.

Below is the message of report clock. XDC file is also attached.

 

BTW, several procedures are used in the coding. That would confuse the analyzer?

 

 

Regards,

 

 

..........................

report_clocks
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
| Date : Mon Feb 26 04:57:52 2018
| Host : DESKTOP-PTK9U8E running 64-bit major release (build 9200)
| Command : report_clocks
| Design : uart
| Device : 7k70t-fbg484
| Speed File : -1 PRODUCTION 1.12 2017-02-17
------------------------------------------------------------------------------------

Clock Report


Attributes
P: Propagated
G: Generated
A: Auto-derived
R: Renamed
V: Virtual
I: Inverted
S: Pin phase-shifted with Latency mode

Clock Period(ns) Waveform(ns) Attributes Sources
clock 10.000 {0.000 5.000} V {}


====================================================
Generated Clocks
====================================================

 

====================================================
User Uncertainty
====================================================

 

====================================================
User Jitter
====================================================

 

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Moderator
Moderator
1,419 Views
Registered: ‎03-16-2017

Re: Why is there a no_clock Check Timing warning?

Hi @robertwilliam

 

It looks like there is no primary clock in your project design. 

 

You can go to constraints wizard in Vivado GUI and add your frequency and clock names, it will create a primary clock as per your frequency requirement on a particular port. (As shown below.) After applying it  reimplement your design and check if it helps or not.

 

Capture.JPG

You can able to see that tool has created a clock constraint with a port as per your requirement. 

 

Regards,

hemangd

 

 

 

 

 

 

 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Historian
Historian
1,414 Views
Registered: ‎01-23-2009

Re: Why is there a no_clock Check Timing warning?

The report_clocks shows only one clock in your system, and it is a virtual clock. What this likely means is that the command you used to create the clock was incorrect.

 

When you create a clock in Vivado, you tell it a number of attributes of the clock; the name, the period, the waveform, and (in this case most importantly) where in your design it is attached to. If you skip this last one, it becomes a virtual clock - it is defined, but not connected to your logic.

 

The no_clock DRC check verifies that a defined clock propagates to every clocked cell in your design. Since your virtual clock is not connected to your design, every clocked cell in your design fails this check.

 

To create the clock correctly, you must connect it to the "clock" port of your design (the port of the top level module named "clock" according to your schematic

 

create_clock -name my_clock -period 10 [get_ports clock]

 

Note that the name of the clock given in the -name option is just a name to be given to the clock object - it is just a name and does not give any information about how the clock is used or what it is connected to. The option at the end (the one without a -<option> before it) specifies the clock attachment point - in this case the port with the name "clock".

 

Avrum