12-18-2013 11:00 PM
I have an input clock on my top as below
T2_CLK_p : in std_logic; T2_CLK_n : in std_logic;
I have a constraint as below
NET "T2_CLK_p" TNM_NET = "T2_CLK_p"; TIMESPEC TS_T2_CLK_p = PERIOD "T2_CLK_p" 3 ns HIGH 50 %; NET "T2_CLK_n" TNM_NET = "T2_CLK_n"; TIMESPEC TS_T2_CLK_n = PERIOD "T2_CLK_n" 3 ns HIGH 50 %;
When I run Trace Report I see some register to register paths as unconstraint path.
The source clock and the destination clock is the same clock which is output of PLL.
What am I doing wrong?
12-18-2013 11:07 PM
12-18-2013 11:38 PM
Also, you don't need to set the period constraint on clk_p and clk_n. Period constraint on clk_p should be enough.
Comment out the clk_n constraint and see if the period constraint propagates through PLL.
01-11-2014 10:44 PM
Have you other FROM TO constraints related?