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999068709169
Explorer
Explorer
9,742 Views
Registered: ‎09-08-2009

Why output of PLLs are Unconstrained Paths

Dear Gurus,

 

I have an input clock on my top as below

 

    T2_CLK_p 			: in std_logic;
    T2_CLK_n 			: in std_logic;

 I have a constraint as below

 

   NET "T2_CLK_p" TNM_NET = "T2_CLK_p";
   TIMESPEC TS_T2_CLK_p = PERIOD "T2_CLK_p" 3 ns HIGH 50 %;
   NET "T2_CLK_n" TNM_NET = "T2_CLK_n";
   TIMESPEC TS_T2_CLK_n = PERIOD "T2_CLK_n" 3 ns HIGH 50 %;

 

When I run Trace Report I see some register to register paths as unconstraint path. 

The source clock and the destination clock is the same clock which is output of PLL.

What am I doing wrong?

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4 Replies
999068709169
Explorer
Explorer
9,738 Views
Registered: ‎09-08-2009

I am using  PlanAhead 14.6, Spartan 6 100 ( XC6SLX100csg484-3)

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smarell
Community Manager
Community Manager
9,735 Views
Registered: ‎07-23-2012

Please check the .bld report and make sure that the clock constraint is propagated through the PLL. Additionally check the clocking interaction report (tsi).
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sampatd
Scholar
Scholar
9,719 Views
Registered: ‎09-05-2011

Also, you don't need to set the period constraint on clk_p and clk_n. Period constraint on clk_p should be enough.

 

Comment out the clk_n constraint and see if the period constraint propagates through PLL. 

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brucey
Xilinx Employee
Xilinx Employee
9,657 Views
Registered: ‎03-24-2010

Have you other FROM TO constraints related?

Regards,
brucey
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