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Visitor orecca
Visitor
6,628 Views
Registered: ‎05-21-2009

Why "Minimum Data Path" delay value is larger than "Maximum Data Path" delay value ?

Hi, all

Something on the timing report that confused me a lot :smileysad:

I found that "Minimum Data Path" value is larger than "Maximum Data Path" 

How can be that happened ?

 

Thanx a million

 

 --- timing constraint setting --

NET "CLK_P" TNM_NET   = "CLK_P";
TIMESPEC "TS_CLK_P"   = PERIOD "CLK_P" 1524 ps HIGH 50%;

NET "IDATA_Q0_P" OFFSET = IN 0.15 VALID 1.52 AFTER "CLK_P";

 

 

--- timing report below --

 

================================================================================
Timing constraint: COMP "IDATA_Q0_P" OFFSET = IN 0.15 ns VALID 1.52 ns AFTER
COMP "CLK_P";

 1 item analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum allowable offset is   1.294ns.
--------------------------------------------------------------------------------
Slack (setup path):     1.144ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IDATA_Q0_P (PAD)
  Destination:          serdes_nd_q0_m (FF)
  Destination Clock:    BUFIO_CLK rising at 0.000ns
  Requirement:          1.374ns
  Data Path Delay:      2.162ns (Levels of Logic = 2)
  Clock Path Delay:     1.957ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: IDATA_Q0_P to serdes_nd_q0_m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y1.I                 Tiopi                 0.991   IDATA_Q0_P
                                                       IDATA_Q0_P
                                                       ibufds_instq0/IBUFDS
    IODELAY_X2Y51.IDATAINnet (fanout=1)        0.000   dt_q0_dly
    IODELAY_X2Y51.DATAOUTTioddo_IDATAIN        0.847   delay_q0
                                                       delay_q0
    ILOGIC_X2Y51.DDLY    net (fanout=1)        0.000   w_IDATA_Q0
    ILOGIC_X2Y51.CLK     Tisdck_DDLY           0.324   serdes_nd_q0_m
                                                       serdes_nd_q0_m
    -------------------------------------------------  ---------------------------
    Total                                      2.162ns (2.162ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: CLK_P to serdes_nd_q0_m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    M1.I                 Tiopi                 0.962   CLK_P
                                                       CLK_P
                                                       ibufds_clock_input/IBUFDS
    BUFIO_X2Y7.I         net (fanout=2)        0.237   CLK
    BUFIO_X2Y7.O         Tbufiocko_O           0.580   bufio_0
                                                       bufio_0
    ILOGIC_X2Y51.CLK     net (fanout=24)       0.178   BUFIO_CLK
    -------------------------------------------------  ---------------------------
    Total                                      1.957ns (1.542ns logic, 0.415ns route)
                                                       (78.8% logic, 21.2% route)

--------------------------------------------------------------------------------
Hold Paths: COMP "IDATA_Q0_P" OFFSET = IN 0.15 ns VALID 1.52 ns AFTER COMP "CLK_P";
--------------------------------------------------------------------------------
Slack (hold path):      0.743ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               IDATA_Q0_P (PAD)
  Destination:          serdes_nd_q0_m (FF)
  Destination Clock:    BUFIO_CLK rising at 0.000ns
  Requirement:          1.374ns
  Data Path Delay:      2.170ns (Levels of Logic = 2)
  Clock Path Delay:     2.776ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path: IDATA_Q0_P to serdes_nd_q0_m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    Y1.I                 Tiopi                 0.951   IDATA_Q0_P
                                                       IDATA_Q0_P
                                                       ibufds_instq0/IBUFDS
    IODELAY_X2Y51.IDATAINnet (fanout=1)        0.000   dt_q0_dly
    IODELAY_X2Y51.DATAOUTTioddo_IDATAIN        1.127   delay_q0
                                                       delay_q0
    ILOGIC_X2Y51.DDLY    net (fanout=1)        0.000   w_IDATA_Q0
    ILOGIC_X2Y51.CLK     Tisckd_DDLY (-Th)    -0.092   serdes_nd_q0_m
                                                       serdes_nd_q0_m
    -------------------------------------------------  ---------------------------
    Total                                      2.170ns (2.170ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: CLK_P to serdes_nd_q0_m
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    M1.I                 Tiopi                 1.004   CLK_P
                                                       CLK_P
                                                       ibufds_clock_input/IBUFDS
    BUFIO_X2Y7.I         net (fanout=2)        0.258   CLK
    BUFIO_X2Y7.O         Tbufiocko_O           1.159   bufio_0
                                                       bufio_0
    ILOGIC_X2Y51.CLK     net (fanout=24)       0.355   BUFIO_CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.776ns (2.163ns logic, 0.613ns route)
                                                       (77.9% logic, 22.1% route)

--------------------------------------------------------------------------------

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Xilinx Employee
Xilinx Employee
6,548 Views
Registered: ‎08-02-2007

Re: Why "Minimum Data Path" delay value is larger than "Maximum Data Path" delay value ?

Hello,

 

This is correct behaviour.

 

Thanks,

Hem. 

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