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vinay1438
Adventurer
Adventurer
7,053 Views
Registered: ‎02-07-2013

Will use of MMCM reduces my frequency of operation

Hello sir, I completed my FFT design which is working at 150MHZ (VERTEX 6), but after instantiation of MMCM my frequency reduces drastically to 30MHZ. Please suggest the mistake I may done.

 

Thanks in advance,

Vinay Kumar Maddala

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4 Replies
hgleamon1
Teacher
Teacher
7,044 Views
Registered: ‎11-14-2011

How do you verify your frequency of operation?

 

What is the role of the MMCM in your design?

 

Have you correctly constrained your input clock?

 

How is the input clock routed to the MMCM, and, if applicable, to other logic?

 

Regards,

 

Howard

 

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"That which we must learn to do, we learn by doing." - Aristotle
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vinay1438
Adventurer
Adventurer
7,039 Views
Registered: ‎02-07-2013

1) Freqency observed after post par.

2) My global clock to the FPGA  is 200MHz, but my design frequency is 150MHz, so I used MMCM.(am I using MMCM properly for this situation).

3) yes

4)directly from external clock

 

 

Thanks,

Vinay Kumar Maddala

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hgleamon1
Teacher
Teacher
7,036 Views
Registered: ‎11-14-2011

Without seeing, or you explaining, the full connections in your system, we can only guess what has happended to your system.

 

If your system runs at 150MHz but you have a 200MHz input clock, how did you verify that the system ran at 150MHz prior to putting in the MMCM? Did you initially constrain your input clock to be 150MHz? Have you now reconstrained it to be 200MHz to match your hardware?

 

Is the 150MHz the only output from your MMCM? Is it correctly buffered (BUFG) to the rest of the logic? How have you verified that your instantiation of the MMCM is correct?

 

What does the clock report state for the two implementations?

 

What does the timing report state for the two implementations? If you have correctly constrained your input clock, this would imply you have timing errors when the maximum frequency is reported as 30MHz. Have you timing errors?

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"That which we must learn to do, we learn by doing." - Aristotle
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avrumw
Guide
Guide
7,022 Views
Registered: ‎01-23-2009

You need to post the failing timing path.

 

My suspicion is that you will find that it is a path between two different clock domains. My guess is that before you used the MMCM the two paths came from two different clock inputs, hence ISE treated them as "unrelated" and the path between them was effectively false.

 

If you then convert that so that both clocks are now being generated by the MMCM, suddenly ISE will see these two clocks as related, and hence will start timing the paths between them. If the ratio of frequencies is not simple, then this will have a drastic effect on the maximum frequency reported by the tools.

 

Avrum

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