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isaac_tejerina
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Registered: ‎06-05-2018

Xilinx ISE 14.7 and Spartan 6 libraries for timing

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Hi all,

 

In our Spartan 6 design we implement an SpaceWire interface. In order to check the correctness of the implementation of clock recovery logic of the SpaceWire, the only way is to extract the timing manually and analyzed using spreadsheet or scripts.

We have some paths where the timing has to be adjusted according to other paths. Use of constraints don't help and It could lead to undesired optimizations.

 

In order to extract the timing there are several possibilities:

- Tcl commands --> Tested but I haven't found much documentation and it doesn't look to be an real option

- PlanAhead -->  This tool freezes in Linux and crashes in Windows.

- FPGA Editor --> It really works to extract the timing of the paths but not for the timing of the cells. But actually, this is the tool we are using.

- Simulation using generated netlist --> It is also possible, and it can be use a backup solution.

 

The real question comes when after detailed analysis, we have confirmed that we have a deviation of more than 1 ns from measurement to the analysis.

We have check the Datasheet and our surprise was to discover that the latest version of the timing reported in DS162 is from 2015 but the latest version of ISE 14.7 is from 2013. Older Data sheet document versions have very different timing values.

 

How can we be certain that the ISE 14.7 uses the final timing values of the reported libraries? Is there any update of the Spartan6 libraries for ISE 14.7?

Any other possibility to analyze the timing?

 

Thank you.

 

Regards,

Isaac.

 

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yashp
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Registered: ‎01-16-2013
Hi,

You can use the speedprint command to get all the timing related information for targeted FPGA.
https://www.xilinx.com/support/answers/6067.html

P.S. TCL is not available with ISE environment.

Apart from taking out the timing numbers use post-route timing simulation this is best way to analyze the design/functionality.

Thanks,
Yash

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yashp
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1,408 Views
Registered: ‎01-16-2013
Hi,

You can use the speedprint command to get all the timing related information for targeted FPGA.
https://www.xilinx.com/support/answers/6067.html

P.S. TCL is not available with ISE environment.

Apart from taking out the timing numbers use post-route timing simulation this is best way to analyze the design/functionality.

Thanks,
Yash

View solution in original post

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isaac_tejerina
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Registered: ‎06-05-2018

 

Using this tool, we can confirm that the timing of the libraries is very similar to the one extracted from the Data sheet document.

 

We can continue our investigation, as it still seems that something in the timing is wrong.

Thank you for the quick answer.

 

PS : TCL commands was of course wrong. I was referring to "timing_analysis" command.

 

Regards,

Isaac.

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