Hi all,
The EDK project I have in hand keeps showing that it is not able parsing the timing constranit (.ptwx, not .ucf file);
and most importantly, it's not able generate any static timing reports.
Is there anything I missed that could that could possibly cause this problem?
The tool version is Xilinx Platform Studio EDK14.4 (I have to use it for maitaining an old project) and the target FPGA is xc6vIx240tff1156-2, I also had the the error message screenshot and the timing constranit which is failed to parse attached as below.
Many thanks!
Best Regards
1 Solution
Accepted Solutions
Found out that there is an option file for "Xilinx Fpga Implementation Flow For Fast Run Time" called fast_runtime.opt; which is under the /etc folder of the EDK project.
One could en/disabled the report generation to enhance the run time through modifying this file, and the EDK project I had in hand happend to have the option disabled as the screenshot below.
After enable the option blocks the EDK project is able to generate timing related reports again, however the .ptwx still have parsing problem (but most importantly I got the static timing report!).
Or one could just use the "Timing Analyzer " tool in "ISE Design Tools/64-bit Tools/Timing Analyzer" specifically generating the timing report.
Found out that there is an option file for "Xilinx Fpga Implementation Flow For Fast Run Time" called fast_runtime.opt; which is under the /etc folder of the EDK project.
One could en/disabled the report generation to enhance the run time through modifying this file, and the EDK project I had in hand happend to have the option disabled as the screenshot below.
After enable the option blocks the EDK project is able to generate timing related reports again, however the .ptwx still have parsing problem (but most importantly I got the static timing report!).
Or one could just use the "Timing Analyzer " tool in "ISE Design Tools/64-bit Tools/Timing Analyzer" specifically generating the timing report.