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Registered: ‎08-23-2011

Xilinx reports high Fmax, but cant PAR for a lower freq



i read online that you can implement your design by ignoring timing constraints and then the tool goes into performance evaluation mode (PEM) and gives the best case achievable in terms of the clk freq for various clock domains. for the design by autoconstraining them.


i did that for a design i have and i get the "best case achievable" in the PAR report is -

clk0 (i/p clk) = 9.351ns (i/p clk going into PLL)

clk1 (derived clk) = 6.22ns (derived clock from PLL)

clk2 (derived clk) = 7.555ns (derived clock from PLL)


however, when i constraint my design (ucf file only has i/p clock constraint of 100M), then the PAR report shows the following -


clk0 = req period = 10ns, actual period = 4ns //100M i/p clk

clk1 = req period = 50ns, actual period = 26.34ns //20M derived clk

clk2 = req period = 12.5ns, actual period = 14.7ns //80M derived clk


so as you can see, the 80M constraint is not met because the actual period > req period, but the PEM mode PAR report said that it can do 7.555ns on that clock which is much less than the 12.5ns that i am setting.


so what changes when i put the i/p timing constraint that causes the 80M clk domain to not meet timing even when in PEM mode, the tool says it can do much faster than that? any suggestions so that i can actually do the speed the PEM says?


I am using ise 14.1.





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