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jansc
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Registered: ‎06-17-2015

Xst:3201 - TIMESPEC 'TS_MySpec' is related to another TIMESPEC which is not defined

Hello,

I try to constrain my system in a Spartan 6 device.

There is an input clock going to a PLL. That input is constrained using PERIOD constrain.

The PLL output goes to a DCO, that enables the flipflops, that are clocked by the same PLL output.

Now I want to constraint the enable flipflops with a multicycle (FROM enable_flop TO enable_flop). While Implementation I get the message from the Subject.

 

My Clk constrain as as followed:

NET "sys_clk_i" LOC = "AB13" |IOSTANDARD = LVCMOS33 |TNM_NET = sys_clk_i;
TIMESPEC TS_sys_clk_i = PERIOD "sys_clk_i" 20.833 ns HIGH 50%;

 

the pll automatically defines the output period to:

TS_mio_GlblClkGen_Clk256M_o_pll

 

I took that automatically constrained period an used it in FROM:TO as followed:

TIMESPEC TS_mio_i2c_en_flops = FROM "GRP_mio_i2c_en_flops" TO "GRP_mio_i2c_en_flops"         TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1;

 

Is there any problem with the usage of the automatically assigned Period constraint?

If yes -> Why, and is there any known workaround?

That period constraint doesn´t appear in the *.ucf file. It appears in the *.pcf file. Maybe there is the Problem?

 

Regards Jan.

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vemulad
Xilinx Employee
Xilinx Employee
11,065 Views
Registered: ‎09-20-2012

Hi,

 

The name of the TIMESPEC of the autogenerated constraint may change with design changes. When it gets changed then your constraint will no more be valid.

 

Try defining constraint at output pin of PLL and then use this user TIMESPEC name in your other constraints.

 

Thanks,

Deepika.

Thanks,
Deepika.
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jansc
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Registered: ‎06-17-2015

I tried to find the PLL-output net with constraints editor, but in the list is no clock net name for that output.

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vemulad
Xilinx Employee
Xilinx Employee
11,051 Views
Registered: ‎09-20-2012

Hi,

 

You can check the net name in "Technology schematic".

 

Thanks,

Deepika.

Thanks,
Deepika.
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jansc
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When I look in Technology Schematic I see that the net name is that, what I added to UCF-File, but in the constraints editor I cant choose that net as "Clock Net". The net comes from the output of a BUFG and I thought by that reason it is a clock net.

When I try to add that constrain without usage of the Constraint editor and after that I open the Constraint editor, the message "Unable to find any TNM group that matches name Clk256M". Please fix this problem.

And the Clock Net Column is empty.

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avrumw
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Registered: ‎01-23-2009

The name of the TIMESPEC of the autogenerated constraint may change with design changes. When it gets changed then your constraint will no more be valid.

 

This isn't true in ISE. The auto generated name of the timespecs in ISE are derived from the structure of the clock - you can see that they are related to the hierarchical instance name and pin name of the clock generating block. These names will not change from tool version to version (and besides, there are no more versions of ISE), and will not change unless you change the hierarchy or instance names of the PLL.

 

It is completely legal to use the auto generated name of the timespec as part of another timespec (as you originally did). Regarding the constraints wizard, I haven't checked recently - but in some versions it did allow you to specify constraints against the auto generated constraint, and in others it didn't. It also could depend on whether you implement your design (i.e. run ngdbuild) before opening the constraint wizard. But even if the wizard doesn't allow it, the constraint is legal.

 

It is not recommended to override the auto generated constraint at the PLL output. This will break the timing relationship between this new clock and the original clocks (or other clocks from the same PLL). While there may be ways to override the clock without breaking the relationship, you still shouldn't do it.

 

I am not following the UCF vs. PCF part of your posting. If you put your constraint in the UCF file, it will be properly processed.

 

Avrum

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jansc
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Registered: ‎06-17-2015

Hello,

first thing I did was to use the autogenerated constraints, but when I did that the message

Xst:3201 - TIMESPEC 'TS_MySpec' is related to another TIMESPEC which is not defined

appered for all elements I specified with constraints, relating to that clock net.

In the output path from the PLL to the pll clocked flops there is a BUFG. 

Can the problem be caused by that fact?

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jansc
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Registered: ‎06-17-2015

I have seen something that can maybe help.

I have seen that the pcf file, containing the autogenerated constraints is produced by the map process, so the autogenerated constraints, I use, are not known at the point where ISE runs the Translate process. They are not contained in the UCF file and I only know those Timenames because I use the constraint editor to select the group elements/specs and than edit them in the UCF text file.

Am I right?

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avrumw
Expert
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Registered: ‎01-23-2009

The automatically generated constraints are created by the ngdbuild process and are stored (originally) in the .ngd file. You can see the creation of the automatically generated constraints by looking at the ngdbuild log file (<project>.bld). It will show you the name of the automatically generated timespecs there.

 

I know that these timespecs can be used in the UCF file - I have done this many times. Even though the automatically generated constraints are not defined in the UCF file, you can use them - the tools will be able to resolve the reference to the automatically generated timespecs when the UCF is processed. I believe the only requirement is that the PERIOD timespec that feeds the input to the MMCM/PLL appear in the UCF prior to trying to reference the automatically generated timespecs.

 

As for the why you are getting the error - I don't know - maybe if you post the entire UCF file and the .bld file, I might be able to see what the problem is. But I am certain that you can use these timepecs in the UCF file.

 

Avrum

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jansc
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Hello,

are you even sure that I can use those constraints (constrained to the PLL output) if there is the BUFG?

That would explain, why those FFs apear in the timegroup I analyzed with timing analyzer, but then I´m really confused why the message appears.

 

My *.ucf (I deleted the commented lines and the LOC - constraints): 

 

#########################################################################################################################################################
# Define period constrain on sys_clk_i pin
#########################################################################################################################################################
NET "sys_clk_i" LOC = "AB13" |IOSTANDARD = LVCMOS33 |TNM_NET = sys_clk_i;
TIMESPEC TS_sys_clk_i = PERIOD "sys_clk_i" 20.833 ns HIGH 50%;

NET "pin_sys_reset_n_i" LOC = "V15" |IOSTANDARD = LVCMOS33 ;
NET "pin_fx2_ifclk_i" LOC = "Y12" |IOSTANDARD = LVCMOS33 |TNM_NET = "pin_fx2_ifclk_i" ;

# 48 MHz external ifclk
TIMESPEC "TS_pin_fx2_ifclk_i" = PERIOD "pin_fx2_ifclk_i" 2000 ns HIGH 50 % ;
#
TIMEGRP "FLAGS" OFFSET = IN 13.5 ns AFTER "pin_fx2_ifclk_i" ;

# external ifclk
NET "pin_fx2_slrd_n_o" OFFSET = OUT 100 ns BEFORE "pin_fx2_ifclk_i" ;
NET "pin_fx2_slwr_n_o" OFFSET = OUT 100 ns BEFORE "pin_fx2_ifclk_i" ;
#

# external ifclk
TIMEGRP "FD" OFFSET = IN 100 ns AFTER "pin_fx2_ifclk_i" ;
TIMEGRP "FD" OFFSET = OUT 100 ns BEFORE "pin_fx2_ifclk_i" ;
#

# SPECIAL STATEMENTS:
NET "trig2" CLOCK_DEDICATED_ROUTE = FALSE; # J-Sc (Error seems to be caused because a BUFGMUX is placed at a NOT DEDECATED CLK PIN)
# PIN "mio_GlblClkGen/buf_pll_ext_o.O" CLOCK_DEDICATED_ROUTE = FALSE;
INST "inst_wb_ma_fx2/*" TNM = wb_ma_adr;
INST "inst_wb_ma_fx2/u_fifo_32_16/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram" TNM = fifo_32_16;
INST "inst_wb_ma_fx2/u_fifo_32_16/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram" TNM = fifo_32_16;
TIMESPEC TS_WISHBONE = FROM "wb_ma_adr" TO "fifo_32_16" TS_sys_clk_i * 2;
TIMESPEC TS_WISHBONE_DAT = FROM "WB_SL_GPIO_FF" TO "fifo_32_16" TS_sys_clk_i * 2;
INST "inst_wb_sl_gpio/*" TNM = WB_SL_GPIO_FF;

##################################################################### Define Groups #####################################################################
# To allow ovaerlapping signal removage, all signals from the Multicycles must be in the period spec
#########################################################################################################################################################
# Define all flops that are driven by the en from DCO in a group
#########################################################################################################################################################
NET "u_mio_a_sci2cTop/mio_sci2c_dco/ClkOut" TNM_NET = GRP_mio_i2c_en_flops;
NET "u_mio_b_FeatConTop/mio_featcon_dco/ClkOut" TNM_NET = GRP_mio_i2c_featcon_en_flops;

#########################################################################################################################################################
# Define From all flops with a DCO enable to all flops (except those in the jtag fifo) with DCO enable with a multicycle of 3 * 256MHz period
#########################################################################################################################################################
TIMESPEC TS_mio_i2c_en_flops = FROM "GRP_mio_i2c_en_flops" TO "GRP_mio_i2c_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1; #11.7187 ns PRIORITY 1;
TIMESPEC TS_mio_i2c_featcon_en_flops = FROM "GRP_mio_i2c_featcon_en_flops" TO "GRP_mio_i2c_featcon_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1; #11.7187 ns PRIORITY 1;

 

 

 

 

and the *.bld file:

 

Release 14.7 ngdbuild P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -filter
iseconfig/filter.filter -intstyle ise -dd _ngo -nt timestamp -uc
M:/1_Firma/Temp/partition_constrain/configuration/mio_reader.ucf -p
xc6slx150-fgg484-3 mio_reader_top.ngc mio_reader_top.ngd

Reading NGO file "M:/1_Firma/Temp/partition_constrain/xilinx/mio_reader_top.ngc"
...
Loading design module
"M:\1_Firma\Temp\partition_constrain\xilinx/fifo_32_16.ngc"...
Loading design module
"M:\1_Firma\Temp\partition_constrain\xilinx/fifo_16_32.ngc"...
Loading design module
"M:\1_Firma\Temp\partition_constrain\xilinx/bram_32x8192.ngc"...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file
"M:/1_Firma/Temp/partition_constrain/configuration/mio_reader.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
INFO:ConstraintSystem:178 - TNM 'sys_clk_i', used in period specification
'TS_sys_clk_i', was traced into PLL_ADV instance PLL_ADV. The following new
TNM groups and period specifications were generated at the PLL_ADV output(s):

CLKOUT1: <TIMESPEC TS_mio_GlblClkGen_sys_clk_o_pll = PERIOD
"mio_GlblClkGen_sys_clk_o_pll" TS_sys_clk_i HIGH 50%>

INFO:ConstraintSystem:178 - TNM 'sys_clk_i', used in period specification
'TS_sys_clk_i', was traced into PLL_ADV instance PLL_ADV. The following new
TNM groups and period specifications were generated at the PLL_ADV output(s):

CLKOUT0: <TIMESPEC TS_mio_GlblClkGen_Clk256M_o_pll = PERIOD
"mio_GlblClkGen_Clk256M_o_pll" TS_sys_clk_i / 5.333333333 HIGH 50%>

WARNING:ConstraintSystem - The Offset constraint <TIMEGRP "FLAGS" OFFSET = IN
13.5 ns AFTER "pin_fx2_ifclk_i" ;>
[M:/1_Firma/Temp/partition_constrain/configuration/mio_reader.ucf(42)], is
specified without a duration. This will result in a lack of hold time checks
in timing reports. If hold time checks are desired a duration value should
be specified following the 'VALID' keyword.

WARNING:ConstraintSystem - The Offset constraint <TIMEGRP "FD" OFFSET = IN 100
ns AFTER "pin_fx2_ifclk_i" ;>
[M:/1_Firma/Temp/partition_constrain/configuration/mio_reader.ucf(73)], is
specified without a duration. This will result in a lack of hold time checks
in timing reports. If hold time checks are desired a duration value should
be specified following the 'VALID' keyword.

Done...

Checking expanded design ...
WARNING:NgdBuild:483 - Attribute "INIT" on
"inst_wb_ma_fx2/inst_fx2_slfifo_ctrl/fifos[0].inst_sync_fifo16/count<0>" is
on the wrong type of object. Please see the Constraints Guide for more
information on this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
"inst_wb_ma_fx2/inst_fx2_slfifo_ctrl/fifos[0].inst_sync_fifo16/count<1>" is
on the wrong type of object. Please see the Constraints Guide for more
information on this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
"inst_wb_ma_fx2/inst_fx2_slfifo_ctrl/fifos[0].inst_sync_fifo16/count<2>" is
on the wrong type of object. Please see the Constraints Guide for more
information on this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
"inst_wb_ma_fx2/inst_fx2_slfifo_ctrl/fifos[0].inst_sync_fifo16/count<3>" is
on the wrong type of object. Please see the Constraints Guide for more
information on this attribute.
WARNING:NgdBuild:470 - bidirect pad net 'ext_con<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'ext_con<2>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<9>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<8>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<7>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<5>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<4>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<2>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<1>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'lpc_con<0>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP9' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP10' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP11' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP12' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP13' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP14' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP15' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP16' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP17' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP18' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP19' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'TP20' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'cryp_mem_sda' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'display_12' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'display_13' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'display_14' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'display_15' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'display_16' has no legal driver

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 36

Total memory usage is 233200 kilobytes

Writing NGD file "mio_reader_top.ngd" ...
Total REAL time to NGDBUILD completion: 7 sec
Total CPU time to NGDBUILD completion: 7 sec

Writing NGDBUILD log file "mio_reader_top.bld"...

 

I would be very happy if you could find anything with those files.

 

Regards and thank you Jan

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avrumw
Expert
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10,720 Views
Registered: ‎01-23-2009

Where are you seeing the error message (which log file) and what is the actual error message.

 

I also wonder about the PRIORITY keyword - that shouldn't be needed, and maybe it is messing things up.

 

Avrum

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graces
Moderator
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10,714 Views
Registered: ‎07-16-2008

The translate log looks fine and the TS_sys_clk_i seems to be correctly processed.

Are you seeing the message in MAP? Did you turn on -global_opt option? If so, try turning it off and see if that eliminates the message.

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jansc
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The message appears in the "map messages".

The "-global_opt option" was set to speed. Now it´s set to "Off". The messages don´t appear now anymore, but the problem stays the same. The particular FFs apear in PERIOD and in FROM:TO constrain...

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avrumw
Expert
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10,694 Views
Registered: ‎01-23-2009

What do you mean by "The particular FFs apear in PERIOD and in FROM:TO constrain". How are you coming to this conclusion?

 

Both the PERIOD and the FROM:TO constraints constrain paths not flip-flops. You have specifically constrained the paths that start from the FFs in the group GRP_mio_i2c_en_flops and end at FFs in the group GRP_mio_i2c_en_flops to be multicycle. This only covers paths that both start and end at the same group. There may well be other paths that start at the group and end somewhere else or that start somewhere else and end at the group that are (correctly) not covered by the FROM:TO timespec.

 

Furthermore, you have two sets of multicycle paths; TS_mio_i2c_en_flops and TS_mio_i2c_featcon_en_flop. Each one specifies paths between their own groups. Notably, the paths (if they exist) between FFs in GRP_mio_i2c_en_flops and FFs in GRP_mio_i2c_featcon_en_flops are not multicycle.

 

As for paths being in two different timespecs; in ISE, this is impossible. By definition, a path can be covered by one and only one timespec...

 

Actually, now that I think of it, I am fairly certain the priority flag is messing things up. By saying PRIORITY 1, you are explicitly saying your multicycle path constraint is lower priority than your PERIOD constraint (the higher the number, the lower the priority - no PRIORITY flag is equivalent to PRIORITY 0, and PRIORITY can be between -100 and 100). So, normally, the FROM:TO constraint would remove paths from the PERIOD timespec and put them in the FROM:TO timespec. But by saying the FROM:TO is lower PRIORITY, it may prevent this from happening. Remove the PRIORITY keyword and see what happens.

 

Lastly, you can check if your group is constructed correctly using the Verbose report from trce (adding the -v flag) - that will list the contents of all the timegroups - you can make sure that the FFs you expect to be in the TNM are actually there.

 

Avrum

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jansc
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Registered: ‎06-17-2015

What do you mean by "The particular FFs apear in PERIOD and in FROM:TO constrain". How are you coming to this conclusion?

When I look in the timegroups those ffs apear in both groups. Now I know that this is ok, because the important thing is the path.

Furthermore, you have two sets of multicycle paths; TS_mio_i2c_en_flops and TS_mio_i2c_featcon_en_flop. Each one specifies paths between their own groups. Notably, the paths (if they exist)...

There are no paths between those groups.

Actually, now that I think of it, I am fairly certain the priority flag is messing things up. By saying PRIORITY 1, you are explicitly saying your multicycle path constraint is lower priority than your PERIOD constraint (the higher the number, the lower the priority - no PRIORITY flag is equivalent to PRIORITY 0, and PRIORITY can be between -100 and 100). So, normally, the FROM:TO constraint would remove paths from the PERIOD timespec and put them in the FROM:TO timespec. But by saying the FROM:TO is lower PRIORITY, it may prevent this from happening. Remove the PRIORITY keyword and see what happens.

Ok, I removed the PRIORITY keywords and it seems that there is no change. Furthermore I read in tsi-report: 

...(lowest to highest precedence):

Unconstrained path analysis

PERIOD or FREQUENCY, allclocknets

PERIOD or FREQUENCY, time group

...

When two or more timing constraints have the same precedence, an optional PRIORITY qualifier can be used

That sounds for me as if there is no relation between the priority of the period and the priority of the FROM:TO path.

Additional I cant understand that the PRIORITY option is given when I shouldn´t use it.

With the PRIORITY, if it would work, things would be much easier.

 

The problem that I really don´t understand is that some paths that are defined by FROM "en_flops" TO "en_flops" apear in the 256MHz Period constrain, while I can see those flops in the "en_flops" group. Should the FROM:TO not be in higher priority?

 

Another thing I observed was, that some of my RAMS that are even displayed in the *.twx-report with (ram) dont apear in the predefined RAMS group.

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jansc
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Here is an example for that strange behaviour:

 

the analysis.twx:

Analysis.twx.png

 

the query.twx:

query.twx.png

 

And here is my complete UCF file:

 

#########################################################################################################################################################
# Define period constrain on sys_clk_i pin
#########################################################################################################################################################
NET "sys_clk_i" LOC = "AB13" |IOSTANDARD = LVCMOS33 | TNM_NET = sys_clk_i;
TIMESPEC TS_sys_clk_i = PERIOD "sys_clk_i" 20.833 ns HIGH 50% PRIORITY 10;

#########################################################################################################################################################
# Define period constrain on trig2 pin
#########################################################################################################################################################
#NET "trig2" TNM_NET = trig2;
#TIMESPEC TS_trig2 = PERIOD "trig2" 20.833 ns HIGH 50% PRIORITY 13;
#########################################################################################################################################################
# Define period constrain on BUFGMUX output
#########################################################################################################################################################
#NET "u_mio_a_gpio_seqTop/MuxClk" TNM_NET = "mio_gpio_MuxClk";
#TIMESPEC TS_mio_gpio_MuxClk = PERIOD "mio_gpio_MuxClk" 3.90625 ns HIGH 50% PRIORITY 10;
#NET "u_mio_a_sci2cTop/MuxClk" TNM_NET = "mio_sci2c_MuxClk";
#TIMESPEC TS_mio_sci2c_MuxClk = PERIOD "mio_sci2c_MuxClk" 3.90625 ns HIGH 50% PRIORITY 10;
#NET "u_mio_a_spiTop/MuxClk" TNM_NET = "mio_spi_MuxClk";
#TIMESPEC TS_mio_spi_MuxClk = PERIOD "mio_spi_MuxClk" 3.90625 ns HIGH 50% PRIORITY 10;
#NET "u_mio_a_swpTop/MuxClk" TNM_NET = "mio_swp_MuxClk";
#TIMESPEC TS_mio_swp_MuxClk = PERIOD "mio_swp_MuxClk" 3.90625 ns HIGH 50% PRIORITY 10;
#NET "u_mio_a_uartTop/MuxClk" TNM_NET = "mio_uart_MuxClk";
#TIMESPEC TS_mio_uart_MuxClk = PERIOD "mio_uart_MuxClk" 3.90625 ns HIGH 50% PRIORITY 10;
NET "pin_sys_reset_n_i" LOC = "V15" |IOSTANDARD = LVCMOS33 ;
NET "pin_fx2_ifclk_i" LOC = "Y12" |IOSTANDARD = LVCMOS33 |TNM_NET = "pin_fx2_ifclk_i" ;


# 48 MHz external ifclk
TIMESPEC "TS_pin_fx2_ifclk_i" = PERIOD "pin_fx2_ifclk_i" 2000 ns HIGH 50 % ;
#
# FX2_FLAGS
NET "pin_fx2_flag_n_i<0>" LOC = "T16 " |TNM = "FLAGS" |IOSTANDARD = LVCMOS33 |PULLDOWN; # FX2_FLAGA
NET "pin_fx2_flag_n_i<1>" LOC = "AB20" |TNM = "FLAGS" |IOSTANDARD = LVCMOS33 |PULLDOWN; # FX2_FLAGB_CTL1
NET "pin_fx2_flag_n_i<2>" LOC = "T15 " |TNM = "FLAGS" |IOSTANDARD = LVCMOS33 |PULLDOWN; # FX2_FLAGC
# external ifclk
TIMEGRP "FLAGS" OFFSET = IN 13.5 ns AFTER "pin_fx2_ifclk_i" ;
#
NET "pin_fx2_sloe_n_o" LOC = "AB15" |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST ;
NET "pin_fx2_slrd_n_o" LOC = "AA16" |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST ;
NET "pin_fx2_slwr_n_o" LOC = "Y15 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST ;
NET "pin_fx2_pktend_n_o" LOC = "AB16" |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST ;
NET "pin_fx2_fifoadr_o<1>" LOC = "T6 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST ;
NET "pin_fx2_fifoadr_o<0>" LOC = "T20 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST ;

# external ifclk
NET "pin_fx2_slrd_n_o" OFFSET = OUT 100 ns BEFORE "pin_fx2_ifclk_i" ;
NET "pin_fx2_slwr_n_o" OFFSET = OUT 100 ns BEFORE "pin_fx2_ifclk_i" ;
#
NET "pin_fx2_fd_io<0>" LOC = "AA20" |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<1>" LOC = "U14 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<2>" LOC = "U13 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<3>" LOC = "AA6 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<4>" LOC = "AB6 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<5>" LOC = "W4 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<6>" LOC = "Y4 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<7>" LOC = "Y7 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<8>" LOC = "V18 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<9>" LOC = "V19 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<10>" LOC = "R15 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<11>" LOC = "V17 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<12>" LOC = "R16 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<13>" LOC = "W17 " |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<14>" LOC = "AA18" |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";
NET "pin_fx2_fd_io<15>" LOC = "AB18" |IOSTANDARD = LVCMOS33 |DRIVE = 16 |SLEW = FAST |TNM = "FD";

# external ifclk
TIMEGRP "FD" OFFSET = IN 100 ns AFTER "pin_fx2_ifclk_i" ;
TIMEGRP "FD" OFFSET = OUT 100 ns BEFORE "pin_fx2_ifclk_i" ;
#
################## ANALOGBOARD ##################
###################################
# global pins for the Analogboard #
###################################
NET "dac_nsync" LOC = "R20" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "dac_sclk" LOC = "W20" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "dac_sdin" LOC = "P18" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST;
NET "dac_sdo" LOC = "D19" |IOSTANDARD = LVCMOS33;
NET "adc_ncs" LOC = "C11" |IOSTANDARD = LVCMOS33;
NET "adc_clk" LOC = "C12" |IOSTANDARD = LVCMOS33;
NET "adc_a<2>" LOC = "D9" |IOSTANDARD = LVCMOS33;
NET "adc_a<1>" LOC = "B10" |IOSTANDARD = LVCMOS33;
NET "adc_a<0>" LOC = "A11" |IOSTANDARD = LVCMOS33;

##########################################
# IO cell pins for the ASCOT Analogboard #
##########################################
#new configuration with associated cell->UserIO
NET "io_adc_douta<7>" LOC = "K18" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<12>" LOC = "D7" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<8>" LOC = "V11" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<1>" LOC = "G16" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<13>" LOC = "U6" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<9>" LOC = "U9" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<2>" LOC = "H19" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<15>" LOC = "C6" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<11>" LOC = "Y3" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<6>" LOC = "H22" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<3>" LOC = "F22" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<14>" LOC = "W11" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<10>" LOC = "W12" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<5>" LOC = "V21" |IOSTANDARD = LVCMOS33;
NET "io_adc_douta<4>" LOC = "U22" |IOSTANDARD = LVCMOS33;

# old configuration
#new configuration with associated cell->UserIO
NET "io_adc_doutb<7>" LOC = "K16" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<12>" LOC = "D8" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<8>" LOC = "T10" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<1>" LOC = "G17" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<13>" LOC = "V5" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<9>" LOC = "V9" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<2>" LOC = "H17" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<15>" LOC = "A6" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<11>" LOC = "A4" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<6>" LOC = "J20" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<3>" LOC = "G20" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<14>" LOC = "AB10" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<10>" LOC = "AA12" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<5>" LOC = "V20" |IOSTANDARD = LVCMOS33;
NET "io_adc_doutb<4>" LOC = "U20" |IOSTANDARD = LVCMOS33;

########################################################################
# Timing specification for the analogboard paths #
########################################################################
TIMESPEC "TS_ANA_O" = FROM FFS TO "ANA_TM_O" 40ns; # TS_ANA_O is the name for the time specification and ANA_TM_O is the group TS_ mast be the prefix for a TIMESPEC name
TIMESPEC "TS_ANA_I" = FROM "ANA_TM_I" TO FFS 40ns;

# old configuration
#new configuration with associated cell->UserIO
NET "io_sel0<7>" LOC = "M16" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<12>" LOC = "C5" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<8>" LOC = "R11" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<1>" LOC = "D20" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<13>" LOC = "T5" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<9>" LOC = "U10" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<2>" LOC = "H16" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<15>" LOC = "A5" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<11>" LOC = "AB2" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<6>" LOC = "G22" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<3>" LOC = "E22" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<14>" LOC = "AB11" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<10>" LOC = "AB14" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<5>" LOC = "U19" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel0<4>" LOC = "T22" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";

# old configuration
#new configuration with associated cell->UserIO
NET "io_sel1<7>" LOC = "M17" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<12>" LOC = "C7" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<8>" LOC = "T11" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<1>" LOC = "F19" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<13>" LOC = "R7" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<9>" LOC = "W10" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<2>" LOC = "H18" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<15>" LOC = "D6" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<11>" LOC = "AA2" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<6>" LOC = "H21" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<3>" LOC = "F21" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<14>" LOC = "Y11" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<10>" LOC = "AA14" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<5>" LOC = "V22" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_sel1<4>" LOC = "T21" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";

# old configuration
#new configuration with associated cell->UserIO
NET "io_dir<7>" LOC = "K19" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<12>" LOC = "R13" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<8>" LOC = "R8" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<1>" LOC = "F17" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<13>" LOC = "Y13" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<9>" LOC = "Y9" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<2>" LOC = "K17" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<15>" LOC = "C8" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<11>" LOC = "A9" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<6>" LOC = "C19" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<3>" LOC = "B22" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<14>" LOC = "Y10" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<10>" LOC = "Y6" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<5>" LOC = "K22" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";
NET "io_dir<4>" LOC = "N22" |IOSTANDARD = LVCMOS33 |DRIVE = 4 |SLEW = FAST |TNM_NET = "ANA_TM_O";

# old configuration
#new configuration with associated cell->UserIO
NET "io_current<7>" LOC = "L19" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<12>" LOC = "T14" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<8>" LOC = "W6" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<1>" LOC = "F16" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<13>" LOC = "W15" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<9>" LOC = "W8" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<2>" LOC = "G19" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<15>" LOC = "B8" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<11>" LOC = "A10" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<6>" LOC = "C20" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<3>" LOC = "D22" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<14>" LOC = "AA8" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<10>" LOC = "AA4" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<5>" LOC = "M22" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_current<4>" LOC = "R22" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";

# old configuration
#new configuration with associated cell->UserIO
NET "io_in<7>" LOC = "K20" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<12>" LOC = "U12" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<8>" LOC = "T8" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<1>" LOC = "F20" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<13>" LOC = "Y14" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<9>" LOC = "W9" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<2>" LOC = "J17" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<15>" LOC = "B6" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<11>" LOC = "A8" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<6>" LOC = "A20" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<3>" LOC = "B21" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<14>" LOC = "AA10" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<10>" LOC = "Y8" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<5>" LOC = "L20" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";
NET "io_in<4>" LOC = "M20" |IOSTANDARD = LVCMOS33 |TNM_NET = "ANA_TM_I";

# old configuration
#new configuration with associated cell->UserIO
NET "io_ccspu_sel0<7>" LOC = "L17" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<12>" LOC = "V13" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<8>" LOC = "V7" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<1>" LOC = "F18" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<13>" LOC = "AB12" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<9>" LOC = "R9" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<2>" LOC = "H20" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<15>" LOC = "A7" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<11>" LOC = "D10" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<6>" LOC = "B20" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<3>" LOC = "C22" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<14>" LOC = "AB9" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<10>" LOC = "AB5" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<5>" LOC = "L22" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel0<4>" LOC = "P22" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;

# old configuration
#new configuration with associated cell->UserIO
NET "io_ccspu_sel1<7>" LOC = "L15" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<12>" LOC = "W13" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<8>" LOC = "T7" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<1>" LOC = "E20" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<13>" LOC = "Y16" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<9>" LOC = "U8" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<2>" LOC = "J16" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<15>" LOC = "C9" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<11>" LOC = "C10" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<6>" LOC = "A21" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<3>" LOC = "D21" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<14>" LOC = "AB8" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<10>" LOC = "AB4" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<5>" LOC = "M21" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "io_ccspu_sel1<4>" LOC = "P21" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;

#####################################
# VCC cell pins for the Analogboard #
#####################################
NET "vcc_adc_douta<0>" LOC = "M18" |IOSTANDARD = LVCMOS33;
NET "vcc_adc_doutb<0>" LOC = "M19" |IOSTANDARD = LVCMOS33;

NET "vcc_sel0<0>" LOC = "N20" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "vcc_sel1<0>" LOC = "N16" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;

NET "vcc_dir<0>" LOC = "P19" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "vcc_current<0>" LOC = "N19" |IOSTANDARD = LVCMOS33;
NET "vcc_in<0>" LOC = "P20" |IOSTANDARD = LVCMOS33;

NET "vcc_fb_sel<0>" LOC = "P17" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;

NET "vcc_cap0<0>" LOC = "Y5" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "vcc_cap1<0>" LOC = "AB3" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;
NET "vcc_cap2<0>" LOC = "W14" |IOSTANDARD = LVCMOS33 |DRIVE = 24 |SLEW = FAST;

#######################
# Extension Connector #
#######################
NET "ext_con<3>" LOC = "G8" |IOSTANDARD = LVCMOS33;
NET "ext_con<2>" LOC = "T19" |IOSTANDARD = LVCMOS33;
NET "ext_con<1>" LOC = "B18" |IOSTANDARD = LVCMOS33;
NET "ext_con<0>" LOC = "A18" |IOSTANDARD = LVCMOS33;

##############
# Testpoints #
##############
NET "TP9" LOC = "G9" |IOSTANDARD = LVCMOS33;
NET "TP10" LOC = "H10" |IOSTANDARD = LVCMOS33;
NET "TP11" LOC = "F8" |IOSTANDARD = LVCMOS33;
NET "TP12" LOC = "F14" |IOSTANDARD = LVCMOS33;
NET "TP13" LOC = "F9" |IOSTANDARD = LVCMOS33;
NET "TP14" LOC = "F10" |IOSTANDARD = LVCMOS33;
NET "TP15" LOC = "E8" |IOSTANDARD = LVCMOS33;
NET "TP16" LOC = "H14" |IOSTANDARD = LVCMOS33; # SSP0_MOSI
NET "TP17" LOC = "G13" |IOSTANDARD = LVCMOS33; # SSP0_MISO
NET "TP18" LOC = "E10" |IOSTANDARD = LVCMOS33;
NET "TP19" LOC = "H13" |IOSTANDARD = LVCMOS33; # SSP0_SSEL
NET "TP20" LOC = "H12" |IOSTANDARD = LVCMOS33; # SSP0_SCK
################## MISCELLANEOUS ##################
#################
# Crypto Memory #
#################
NET "cryp_mem_sda" LOC = "D11" |IOSTANDARD = LVCMOS33;
NET "crypt_mem_scl" LOC = "C13" |IOSTANDARD = LVCMOS33;

###################
# Flash interface #
###################
NET "pin_flash_s_n_o" LOC = "B14 " |IOSTANDARD = LVCMOS33 ; #SPI_CS
NET "pin_flash_c_o" LOC = "A14 " |IOSTANDARD = LVCMOS33 ; #SPI_SCK
NET "pin_flash_d_o" LOC = "A15 " |IOSTANDARD = LVCMOS33 ; #SPI_SI
NET "pin_flash_q_i" LOC = "A16 " |IOSTANDARD = LVCMOS33 ; #SPI_SO
#################
# Display ports #
#################
NET "pin_RS" LOC = "A17" |IOSTANDARD = LVCMOS33 ; # Display_11
NET "pin_RW" LOC = "D17" |IOSTANDARD = LVCMOS33 ; # Display_8
NET "pin_E" LOC = "C16" |IOSTANDARD = LVCMOS33 ; # Display_10
NET "pin_DB<7>" LOC = "C15" |IOSTANDARD = LVCMOS33 ; # Display_6
NET "pin_DB<6>" LOC = "E16" |IOSTANDARD = LVCMOS33 ; # Display_7
NET "pin_DB<5>" LOC = "B12" |IOSTANDARD = LVCMOS33 ; # Display_4
NET "pin_DB<4>" LOC = "D15" |IOSTANDARD = LVCMOS33 ; # Display_5
NET "pin_DB<3>" LOC = "A13" |IOSTANDARD = LVCMOS33 ; # Display_2
NET "pin_DB<2>" LOC = "A12" |IOSTANDARD = LVCMOS33 ; # Display_3
NET "pin_DB<1>" LOC = "C14" |IOSTANDARD = LVCMOS33 ; # Display_0
NET "pin_DB<0>" LOC = "D14" |IOSTANDARD = LVCMOS33 ; # Display_1
NET "pin_BL_CONTROL" LOC = "B16" |IOSTANDARD = LVCMOS33 |DRIVE = 2 ; # Display_9
NET "display_12" LOC = "C17" |IOSTANDARD = LVCMOS33;
NET "display_13" LOC = "F12" |IOSTANDARD = LVCMOS33;
NET "display_14" LOC = "E12" |IOSTANDARD = LVCMOS33;
NET "display_15" LOC = "D13" |IOSTANDARD = LVCMOS33;
NET "display_16" LOC = "D12" |IOSTANDARD = LVCMOS33;

################################
# LPC Connections (LPC_Future) #
################################
NET "lpc_con<9>" LOC = "U16" |IOSTANDARD = LVCMOS33;
NET "lpc_con<8>" LOC = "T17" |IOSTANDARD = LVCMOS33;
NET "lpc_con<7>" LOC = "U17" |IOSTANDARD = LVCMOS33;
NET "lpc_con<6>" LOC = "T18" |IOSTANDARD = LVCMOS33;
NET "lpc_con<5>" LOC = "Y18" |IOSTANDARD = LVCMOS33;
NET "lpc_con<4>" LOC = "W18" |IOSTANDARD = LVCMOS33;
NET "lpc_con<3>" LOC = "AA21" |IOSTANDARD = LVCMOS33;
NET "lpc_con<2>" LOC = "Y19" |IOSTANDARD = LVCMOS33;
NET "lpc_con<1>" LOC = "AB19" |IOSTANDARD = LVCMOS33;
NET "lpc_con<0>" LOC = "AB21" |IOSTANDARD = LVCMOS33;

###############
# BNC Trigger #
###############
NET "trig1" LOC = "Y17" |IOSTANDARD = LVCMOS33;
NET "trig2" LOC = "AB17" |IOSTANDARD = LVCMOS33;

# SPECIAL STATEMENTS:
NET "trig2" CLOCK_DEDICATED_ROUTE = FALSE; # J-Sc (Error seems to be caused because a BUFGMUX is placed at a NOT DEDECATED CLK PIN)
# PIN "mio_GlblClkGen/buf_pll_ext_o.O" CLOCK_DEDICATED_ROUTE = FALSE;
INST "inst_wb_ma_fx2/*" TNM = wb_ma_adr;
INST "inst_wb_ma_fx2/u_fifo_32_16/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram" TNM = fifo_32_16;
INST "inst_wb_ma_fx2/u_fifo_32_16/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/s6_noinit.ram/SDP.SIMPLE_PRIM18.ram" TNM = fifo_32_16;
TIMESPEC TS_WISHBONE = FROM "wb_ma_adr" TO "fifo_32_16" TS_sys_clk_i * 2;
TIMESPEC TS_WISHBONE_DAT = FROM "WB_SL_GPIO_FF" TO "fifo_32_16" TS_sys_clk_i * 2;
INST "inst_wb_sl_gpio/*" TNM = WB_SL_GPIO_FF;

##################################################################### Define Groups #####################################################################
# To allow ovaerlapping signal removage, all signals from the Multicycles must be in the period spec
#########################################################################################################################################################
# Define all flops that are driven by the en from DCO in a group
#########################################################################################################################################################
NET "u_mio_a_sci2cTop/mio_sci2c_dco/ClkOut" TNM_NET = GRP_mio_i2c_en_flops;
NET "u_mio_b_FeatConTop/mio_featcon_dco/ClkOut" TNM_NET = GRP_mio_i2c_featcon_en_flops;
NET "u_mio_a_spiTop/mio_spi_dco/ClkOut" TNM_NET = GRP_mio_spi_en_flops;
NET "u_mio_b_jtagTop/mio_jtag_dco/ClkOut" TNM_NET = GRP_mio_jtag_en_flops_incl_fifo;
NET "u_mio_a_uartTop/mio_uart_dco/ClkOut" TNM_NET = GRP_mio_uart_en_flops;
NET "u_mio_a_swpTop/mio_swp_dco/ClkOut" TNM_NET = GRP_mio_swp_en_flops;
#NET "u_mio_a_swpTop/swp_FSM/u_mio_swp_frontend/mio_swp_swp_clk_Gen/DivClk" TNM_NET = GRP_mio_swp_en_flops;
NET "u_mio_a_gpio_seqTop/mio_gpio_seq_dco/ClkOut" TNM_NET = GRP_mio_gpio_en_flops_incl_fifo;

#########################################################################################################################################################
# Define jtag fifo enable flops in a group
#########################################################################################################################################################
NET "u_mio_b_jtagTop/Memory/GetNewData1cyc" TNM_NET = GRP_fifo_GetNew;
NET "u_mio_b_jtagTop/Memory/GetNewInstr1cyc" TNM_NET = GRP_fifo_GetNew;

#########################################################################################################################################################
# Define gpio fifo enable flops in a group
#########################################################################################################################################################
NET "u_mio_a_gpio_seqTop/u_gpio_seq/FifoWtGEn" TNM_NET = GRP_fifo_en;
NET "u_mio_a_gpio_seqTop/u_gpio_seq/FifoGtWEn" TNM_NET = GRP_fifo_en;

#########################################################################################################################################################
# Define all 48MHz clocked flops in a group
#########################################################################################################################################################
TIMEGRP "Clk48M_flops" = RISING "mio_GlblClkGen_sys_clk_o_pll";

#########################################################################################################################################################
# Define all 256MHz clocked flops
#########################################################################################################################################################
TIMEGRP "Clk256M_flops" = RISING "mio_GlblClkGen_Clk256M_o_pll";

#########################################################################################################################################################
# Define all enable flops in jtag FSM that are driven by the en from DCO in a group
#########################################################################################################################################################
TIMEGRP "GRP_mio_jtag_en_flops" = "GRP_mio_jtag_en_flops_incl_fifo" EXCEPT "GRP_fifo_GetNew";

#########################################################################################################################################################
# Define all enable flops in gpio FSM that are driven by the en from DCO in a group
#########################################################################################################################################################
TIMEGRP "GRP_mio_gpio_en_flops" = "GRP_mio_gpio_en_flops_incl_fifo" EXCEPT "GRP_fifo_en";

#########################################################################################################################################################
# Define the DCO flop, driven by the Clk Counter as a group
#########################################################################################################################################################
NET "u_mio_a_sci2cTop/mio_sci2c_dco/ClkCnt<0>" TNM_NET = GRP_i2c_dco_out;
NET "u_mio_b_FeatConTop/mio_featcon_dco/ClkCnt<0>" TNM_NET = GRP_i2c_featcon_doc_out;
NET "u_mio_a_spiTop/mio_spi_dco/ClkCnt<0>" TNM_NET = GRP_spi_dco_out;
NET "u_mio_b_jtagTop/mio_jtag_dco/ClkCnt<0>" TNM_NET = GRP_jtag_dco_out;
NET "u_mio_a_uartTop/mio_uart_dco/ClkCnt<0>" TNM_NET = GRP_uart_dco_out;
NET "u_mio_a_swpTop/mio_swp_dco/ClkCnt<0>" TNM_NET = GRP_swp_dco_out;
#NET "u_mio_a_swpTop/swp_FSM/u_mio_swp_frontend/mio_swp_swp_clk_Gen/ClkCnt<0>" TNM_NET = GRP_swp_dco_out;
NET "u_mio_a_gpio_seqTop/mio_gpio_seq_dco/ClkCnt<0>" TNM_NET = GRP_gpio_dco_out;

#########################################################################################################################################################
# Define an Time group that includes all flops except the DCO flops and fifo internal flops
#########################################################################################################################################################
TIMEGRP "GRP_mio_i2c_Clk256M_flops_except_DCO" = "Clk256M_flops" EXCEPT "GRP_i2c_dco_out";
TIMEGRP "GRP_mio_i2c_featcon_Clk256M_flops_except_DCO" = "Clk256M_flops" EXCEPT "GRP_i2c_featcon_doc_out";
TIMEGRP "GRP_mio_spi_Clk256M_flops_except_DCO" = "Clk256M_flops" EXCEPT "GRP_spi_dco_out";
TIMEGRP "GRP_mio_jtag_Clk256M_flops_except_DCO_FIFO" = "Clk256M_flops" EXCEPT "GRP_jtag_dco_out" "GRP_fifo_GetNew";
TIMEGRP "GRP_mio_uart_Clk256M_flops_except_DCO" = "Clk256M_flops" EXCEPT "GRP_uart_dco_out";
TIMEGRP "GRP_mio_swp_Clk256M_flops_except_DCO_swp_clk" = "Clk256M_flops" EXCEPT "GRP_swp_dco_out" "GRP_swp_swp_clk_flop";
TIMEGRP "GRP_mio_gpio_Clk256M_flops_except_DCO_FIFO" = "Clk256M_flops" EXCEPT "GRP_gpio_dco_out" "GRP_fifo_en";

#########################################################################################################################################################
# Define an Time group that includes the flops clocked by swp_clk
#########################################################################################################################################################
TIMEGRP "GRP_swp_swp_clk_flop" = FFS("u_mio_a_swpTop/swp_FSM/u_mio_swp_frontend/mio_swp_swp_clk_Gen/DivClk");

#########################################################################################################################################################
# Define From all flops with a DCO enable to all flops (except those in the jtag fifo) with DCO enable with a multicycle of 3 * 256MHz period
#########################################################################################################################################################
TIMESPEC TS_mio_i2c_en_flops = FROM "GRP_mio_i2c_en_flops" TO "GRP_mio_i2c_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1;
TIMESPEC TS_mio_i2c_featcon_en_flops = FROM "GRP_mio_i2c_featcon_en_flops" TO "GRP_mio_i2c_featcon_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1;
TIMESPEC TS_mio_spi_en_flops = FROM "GRP_mio_spi_en_flops" TO "GRP_mio_spi_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1;
TIMESPEC TS_mio_jtag_en_flops = FROM "GRP_mio_jtag_en_flops" TO "GRP_mio_jtag_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1;
TIMESPEC TS_mio_uart_en_flops = FROM "GRP_mio_uart_en_flops" TO "GRP_mio_uart_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1;
TIMESPEC TS_mio_swp_en_flops = FROM "GRP_mio_swp_en_flops" TO "GRP_mio_swp_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1;
TIMESPEC TS_mio_gpio_en_flops = FROM "GRP_mio_gpio_en_flops" TO "GRP_mio_gpio_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 1;

#########################################################################################################################################################
# Define from all RAMs to DCO driven flops with a multicycle of 3 * 256MHz period
#########################################################################################################################################################
TIMESPEC TS_mio_i2c_ram_en = FROM "RAMS" TO "GRP_mio_i2c_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_i2c_featcon_ram_en = FROM "RAMS" TO "GRP_mio_i2c_featcon_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_spi_ram_en = FROM "RAMS" TO "GRP_mio_spi_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_jtag_ram_en = FROM "RAMS" TO "GRP_mio_jtag_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_uart_ram_en = FROM "RAMS" TO "GRP_mio_uart_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_swp_ram_en = FROM "RAMS" TO "GRP_mio_swp_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;

#########################################################################################################################################################
# Define from all DCO driven flops to all RAMs with a multicycle of 3 * 256MHz period
#########################################################################################################################################################
TIMESPEC TS_mio_i2c_en_ram = FROM "GRP_mio_i2c_en_flops" TO "RAMS" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_i2c_featcon_en_ram = FROM "GRP_mio_i2c_featcon_en_flops" TO "RAMS" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_spi_en_ram = FROM "GRP_mio_spi_en_flops" TO "RAMS" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_jtag_en_ram = FROM "GRP_mio_jtag_en_flops" TO "RAMS" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_uart_en_ram = FROM "GRP_mio_uart_en_flops" TO "RAMS" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;
TIMESPEC TS_mio_swp_en_ram = FROM "GRP_mio_swp_en_flops" TO "RAMS" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 2;

#########################################################################################################################################################
# Define from all DCO driven flops to all flops (except jtag fifo enables) with a multicycle of 3 * 256MHz period
#########################################################################################################################################################
TIMESPEC TS_mio_i2c_en_ffs48M = FROM "GRP_mio_i2c_en_flops" TO "Clk48M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_i2c_featcon_en_ffs48M = FROM "GRP_mio_i2c_featcon_en_flops" TO "Clk48M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_spi_en_ffs48M = FROM "GRP_mio_spi_en_flops" TO "Clk48M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_jtag_en_ffs48M = FROM "GRP_mio_jtag_en_flops" TO "Clk48M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_uart_en_ffs48M = FROM "GRP_mio_uart_en_flops" TO "Clk48M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_swp_en_ffs48M = FROM "GRP_mio_swp_en_flops" TO "Clk48M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_gpio_en_ffs48M = FROM "GRP_mio_gpio_en_flops" TO "Clk48M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 DATAPATHONLY PRIORITY 3;

#########################################################################################################################################################
# Define from all flops EXCEPT the DCO flop and the fifo internal flops to the DCO driven flops with a multicycle of 3 * 256MHz period
#########################################################################################################################################################
TIMESPEC TS_mio_i2c_ffs48M_en = FROM "Clk48M_flops" TO "GRP_mio_i2c_en_flops" TS_sys_clk_i DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_i2c_featcon_ffs48M_en = FROM "Clk48M_flops" TO "GRP_mio_i2c_featcon_en_flops" TS_sys_clk_i DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_spi_ffs48M_en = FROM "Clk48M_flops" TO "GRP_mio_spi_en_flops" TS_sys_clk_i DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_jtag_ffs48M_en = FROM "Clk48M_flops" TO "GRP_mio_jtag_en_flops" TS_sys_clk_i DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_uart_ffs48M_en = FROM "Clk48M_flops" TO "GRP_mio_uart_en_flops" TS_sys_clk_i DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_swp_ffs48M_en = FROM "Clk48M_flops" TO "GRP_mio_swp_en_flops" TS_sys_clk_i DATAPATHONLY PRIORITY 3;
TIMESPEC TS_mio_gpio_ffs48M_en = FROM "Clk48M_flops" TO "GRP_mio_gpio_en_flops" TS_sys_clk_i DATAPATHONLY PRIORITY 3;

#########################################################################################################################################################
# Define from all flops EXCEPT the DCO flop and the fifo internal flops to the DCO driven flops with a multicycle of 3 * 256MHz period
#########################################################################################################################################################
TIMESPEC TS_mio_i2c_en_ffs256M = FROM "GRP_mio_i2c_en_flops" TO "Clk256M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_i2c_featcon_en_ffs256M = FROM "GRP_mio_i2c_featcon_en_flops" TO "Clk256M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_spi_en_ffs256M = FROM "GRP_mio_spi_en_flops" TO "Clk256M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_jtag_en_ffs256M = FROM "GRP_mio_jtag_en_flops" TO "Clk256M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_uart_en_ffs256M = FROM "GRP_mio_uart_en_flops" TO "Clk256M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_swp_en_ffs256M = FROM "GRP_mio_swp_en_flops" TO "Clk256M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_gpio_en_ffs256M = FROM "GRP_mio_gpio_en_flops" TO "Clk256M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;

#########################################################################################################################################################
# Define from all flops EXCEPT the DCO flop and the fifo internal flops to the DCO driven flops with a multicycle of 3 * 256MHz period
#########################################################################################################################################################
TIMESPEC TS_mio_i2c_ffs256M_en = FROM "GRP_mio_i2c_Clk256M_flops_except_DCO" TO "GRP_mio_i2c_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_i2c_featcon_ffs256M_en = FROM "GRP_mio_i2c_featcon_Clk256M_flops_except_DCO" TO "GRP_mio_i2c_featcon_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_spi_ffs256M_en = FROM "GRP_mio_spi_Clk256M_flops_except_DCO" TO "GRP_mio_spi_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_jtag_ffs256M_en = FROM "GRP_mio_jtag_Clk256M_flops_except_DCO_FIFO" TO "GRP_mio_jtag_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_uart_ffs256M_en = FROM "GRP_mio_uart_Clk256M_flops_except_DCO" TO "GRP_mio_uart_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_swp_ffs256M_en = FROM "GRP_mio_swp_Clk256M_flops_except_DCO_swp_clk" TO "GRP_mio_swp_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;
TIMESPEC TS_mio_gpio_ffs256M_en = FROM "GRP_mio_gpio_Clk256M_flops_except_DCO_FIFO" TO "GRP_mio_gpio_en_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 PRIORITY 3;

#########################################################################################################################################################
# Define from all 48MHz clocked flops to all High Clocked flops with a multicycle of 1*48MHz period (Data path only)
#########################################################################################################################################################
TIMESPEC TS_flops48Mto256M = FROM "Clk48M_flops" TO "Clk256M_flops" TS_sys_clk_i DATAPATHONLY PRIORITY 4;

#########################################################################################################################################################
# Define from all High clocked flops to all 48MHz clocked flops with a multicycle of 3 * 256MHz period (Data path only)
#########################################################################################################################################################
TIMESPEC TS_flops256Mto48M = FROM "Clk256M_flops" TO "Clk48M_flops" TS_mio_GlblClkGen_Clk256M_o_pll * 3 DATAPATHONLY PRIORITY 4;

 

 

 

 

 


#########################################################################################################################################################
# Define flops in the jtag fifos with a multicycle of 2 * 48MHz period (from fifo generator documentation: pg057-fifo-generator.pdf)
#########################################################################################################################################################
#### NET "u_mio_b_jtagTop/Memory/u_FifoData/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc*" MAXDELAY = 41.6666 ns;
#### NET "u_mio_b_jtagTop/Memory/u_FifoIfInstr/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_gc*" MAXDELAY = 41.6666 ns;
#### NET "u_mio_b_jtagTop/Memory/u_FifoData/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc*" MAXDELAY = 41.6666 ns;
#### NET "u_mio_b_jtagTop/Memory/u_FifoIfInstr/U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_gc*" MAXDELAY = 41.6666 ns;
#TIMEGRP "GRP_mio_gpio_register_out" = FFS("u_mio_a_gpio_seqTop/u_mio_a_gpio_seqMemory/u_uart_WB_Registers/RegOutInternal*");
#TIMEGRP "GRP_mio_i2c_register_out" = FFS("u_mio_a_sci2cTop/Memory/u_sci2c_WB_Registers/RegOutInternal*");
#TIMEGRP "GRP_mio_spi_register_out" = FFS("u_mio_a_spiTop/Memory/u_spi_WB_Registers/RegOutInternal*");
#TIMEGRP "GRP_mio_uart_register_out" = FFS("u_mio_a_uartTop/Memory/u_uart_WB_Registers/RegOutInternal*");
#TIMEGRP "GRP_mio_swp_register_out" = FFS("u_mio_a_swpTop/Memory/u_swp_WB_Registers/RegOutInternal*");
#TIMEGRP "GRP_mio_jtag_register_out" = FFS("u_mio_b_jtagTop/Memory/u_jtag_WB_Registers/RegOutInternal*");
#TIMEGRP "GRP_mio_i2c_featcon_register_out" = FFS("u_mio_b_FeatConTop/Memory/u_FeatCon_WB_Registers/RegOutInternal*");

 

Regards Jan

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avrumw
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Registered: ‎01-23-2009

The problem that I really don´t understand is that some paths that are defined by FROM "en_flops" TO "en_flops" apear in the 256MHz Period constrain, while I can see those flops in the "en_flops" group. Should the FROM:TO not be in higher priority?

 

Maybe you can post an example of this, although without your design, it will be impossible to really debug this.

 

I have always stayed away from the

 

NET <netname> TNM = <timegroup>;

 

format (or the same with PIN and <pinname>), except when the net/pin is a clock.

 

This format identifies members of the time group as being clocked elements that can be combinatorially reached by the specified pin/net. When the net/pin is a clock, this is clear and cannot be changed by the tool. However, when it is a data signal like you are using (in this case an enable), I am worried as to how logic optimization can change the propagation of the net/pin. I have definitely seen this format include things in the group that shouldn't be included. In some instances, the logic that generates the net/pin specified may end up using the net/pin as part of the generation due to resource sharing, which can get part of the generating circuit into the TNM (which is completely wrong). I have also worried about the converse - what happens if (for example) the generating flip-flop is replicated by synthesis - will only some of the loads get put into the group?

 

Again, you should check the verbose report in the trce output to make sure that all of the flip-flops ended up in the group. If not, that would explain why some paths that you expected to be covered weren't. Then you need to figure out why they didn't get into the group and how to fix it...

 

Avrum

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avrumw
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Registered: ‎01-23-2009

Hmmm... That's definitely odd...

 

So, the start and endpoint are in the TNM...

 

Does the tool acknowledge the TS_mio_spi_en_flops Timespec? Are there paths in it? Do the paths that exist there correspond to flip-flops in the GRP_mio_spi_en_flops group?

 

Nothing I can see should do this. I generally do not use PRIORITY keywords (except under very specific conditions), and I am puzzled as to why the RAMs need to be done separately (I see lots of constraints on the RAMs, and one of your earlier posts mentioned something about the predefined RAMS group), but based on what you have shown here, the path should be covered by the FROM TO.

 

While it shouldn't be a problem, just to rule out the relationship to the automatically generated TIMESPEC, (just as a test) you could change the FROM TO to be

 

TIMESPEC TS_mio_spi_en_flops = FROM "GRP_mio_spi_en_flops" TO "GRP_mio_spi_en_flops" 100 ns;

 

(again, just as a test - this is not a correct constraint for the path) and see if that changes anything.

 

Other than that, I don't have anything to suggest...

 

Avrum

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jansc
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Registered: ‎06-17-2015

Hello,

to change the FROM:TO-Delays to a absolute number didn´t solved my problem. It is still the same behaviour.

To delete PRIORITY keywords or to delete the TNM groups didn´t help either.

Is there any tool or option that can show me how ISE decides which patch is assigned to which constraint?

I´d really like to know, why some of those path apear in the 256M period constraint. 

As seen, the en_flops group isn´t empty and the paths en_flop->en_flop mustn´t be in the period group, because source and destination flops are in the en_group. And in tsi report for excample I can see that from the period constrain, some path (15124 paths) are removed by spi_en_flops group, but some else are obviously not.

How can I go deeper into this problem?

I need to know why things happen as they happen.

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avrumw
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Registered: ‎01-23-2009

The only way to see what path gets covered by what constraint is the timing report. But to really see it, you will have to turn up the number of paths per constraint reported, which will generate a huge file...

 

I don't think there is any more information on how paths are assigned to timespecs - its supposed to be relatively simple - what you are seeing shouldn't happen.

 

The only other suggestion I have is to rebuild the project from scratch. A long time ago, I saw some odd behavior from ngdbuild where it somehow retained state information from run to run - constraints that were no longer in the UCF somehow stuck around. Even "cleaning" the project wasn't sufficient to remove the behavior.

 

I don't know how your build works, but to do this you would need to really start from scratch - start a new project, import all your RTL and UCF files and build clean to see if you get the same thing. Its a pretty long shot, though...

 

Other than that, I have no suggestions. What you are seeing looks like a bug, but there must be something that is causing it. Without seeing the entire project (and possibly even with seeing the entire design), there is nothing more that I can suggest.

 

Avrum

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henkpeters
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Registered: ‎12-13-2013

I have the same problem.

I got these messages for the first time when I changed the -global_opt to Area.

Map.exe even crashes sometimes.

When turning this option off the problem disappears, but then Place & Route cannot complete.

 

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