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794 Views
Registered: ‎12-01-2016

ZYNQ QSPI and UART IP timing violation

Hi

 

I am using 7Z045 -2.

In my project, I instantiate one ARM core, one AXI interconnect, one QSPI and one UART.

 

But both UART and QSPI have timing violation.

 

From :design_1_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/lib_fifo_instance.USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc1.count_d3_reg[1]/C

 

To : design_1_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/lib_fifo_instance.USE_2N_DEPTH.V6_S6_AND_LATER.I_ASYNC_FIFO_BRAM/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/WADR1

 

Slack   -0.05

 

From : design_1_i/UART_TOP/UART0/U0/bus2ip_reset_int_core_reg/C

To:      design_1_i/UART_TOP/UART0/U0/XUART_I_1/UART16550_I_1/NO_EXTERNAL_XIN.ODDR2_GEN.BAUD_FF/R

Slack: -0.31

 

Are these issues which can be ignored? Why?

 

Thanks.

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2 Replies
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744 Views
Registered: ‎12-01-2016

Re: ZYNQ QSPI and UART IP timing violation

Moreover, I am using Vivado 2017.4

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Moderator
Moderator
732 Views
Registered: ‎01-16-2013

Re: ZYNQ QSPI and UART IP timing violation

Hi,

 

Of course this is issue in timing (requirement of your design did not met) and you cannot simply overlook. Every design has to be timing closed before going on board.

 

To know whether this is issue with valid data paths or with constraints; Can you please share the detailed timing report (post-route)? It will be helpful to analyze the paths and provide the further suggestions.

 

Thanks,
Yash

 

 

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