12-20-2018 01:58 PM - edited 12-20-2018 02:04 PM
I'm using a Zynq US+ part and have implemented an GEM (Gigabit Ethernet Mac) interface using using EMIO. I've enabled the MDIO interface as well. The zynq ip block MDIO signals are routed to a xilinx PCS/PMA Ethernet core for GMII <-> SGMII conversion. After implementation i get 2 critical warnings related to the zynq MDIO connections.
1. a "no_clock" on design_wrapper/design_i/zynq_ultra_ps/inst/PS8_i/EMIOENET1MDIOMDC
2. a "unconstrained_internal_endpoints" (specifically for maximum delay) on design_wrapper/design_i/zynq_ultra_ps/inst/PS8_i/EMIOENET1MDIOI
The zynq ps is the Master of the MDIO inteface and I would expect it to be the provider of whatever constraints are necessary, especially in terms of the clock as I have no control of the rate on the PL side.
Should I just ignore these or what can I do to properly constrain the design?
04-08-2020 03:52 PM
For other Customers experiencing this issue,
This issue was fixed in Vivado 2019.2.
As a workaround, please manually create the clock constraint using the following command:
create_clock -period 400.000 -name mdio_mdc_clock [get_pins design_1_i/zynq_ultra_ps_e_0/U0/PS8_i/EMIOENET0MDIOMDC]
After that, please run implementation again and generate a new check timing report to verify the workaround corrected the issue.
Thank you,
03-18-2019 08:31 AM - edited 03-18-2019 08:31 AM
I have the same issue. And if you constrain the path to the fpga pin with -datapath_only:
set_max_delay -datapath_only -from [get_pins {design_1_i/zynq_ultra_ps_e_0/U0/PS8_i/EMIOENET1MDIOTN design_1_i/zynq_ultra_ps_e_0/U0/PS8_i/EMIOENET1MDIOTN}] -to [get_ports {mdio_enet1_mdio_io_p}] 9.0
you get a clock segmentation warning.
What is the proper way to do this?
Thanks
04-08-2020 03:52 PM
For other Customers experiencing this issue,
This issue was fixed in Vivado 2019.2.
As a workaround, please manually create the clock constraint using the following command:
create_clock -period 400.000 -name mdio_mdc_clock [get_pins design_1_i/zynq_ultra_ps_e_0/U0/PS8_i/EMIOENET0MDIOMDC]
After that, please run implementation again and generate a new check timing report to verify the workaround corrected the issue.
Thank you,