I'm using a Zynq US+ part and have implemented an GEM (Gigabit Ethernet Mac) interface using using EMIO. I've enabled the MDIO interface as well. The zynq ip block MDIO signals are routed to a xilinx PCS/PMA Ethernet core for GMII <-> SGMII conversion. After implementation i get 2 critical warnings related to the zynq MDIO connections.
1. a "no_clock" on design_wrapper/design_i/zynq_ultra_ps/inst/PS8_i/EMIOENET1MDIOMDC
2. a "unconstrained_internal_endpoints" (specifically for maximum delay) on design_wrapper/design_i/zynq_ultra_ps/inst/PS8_i/EMIOENET1MDIOI
The zynq ps is the Master of the MDIO inteface and I would expect it to be the provider of whatever constraints are necessary, especially in terms of the clock as I have no control of the rate on the PL side.
Should I just ignore these or what can I do to properly constrain the design?
