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Bareil761
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Registered: ‎06-04-2020

Zynq Z-7014 ok?

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Hi all,

want to use a Z-7014 (speed grade 1C) to interface with an AD9284. The ADC (AD9284) will be running at 212.5MHz DDR using a clock that is synchronous to the output of the ADC. So the 8 lines of the ADC are in sync with the clock line.

The skew between DCO and data is -280ps/+100ps, with a bit period of 1/(2*212.5MHz)=2.35ns. Out of 2.35ns I lose 0.38ns in uncertainty, resulting in a stable data valid period of only 1.97ns.

 

Looking at the DC-AC characteristics of the Zynq, I am not sure it'll work. However, there are so many numbers in that datasheet I really am not sure which one to consider and also what it includes in terms of incertitudes. I think the FPGA I am refering to has a setup and hold of TPSCS/TPHCS –0.38/1.86 which gives a valid window of 1.48ns which in theory is enough since I have 1.97ns?

Am I missing something?

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avrumw
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Guide
170 Views
Registered: ‎01-23-2009

Good job!

Yes, you have analyzed this correctly. With a window of 1.97ns you should be able to do static capture of the interface using "ChipSync" clocking (using the BUFIO and BUFR - or just the BUFR only). And the Tpscs/Tphcs are the correct numbers to be looking at. A small word of warning, though, these numbers, while in the right ballpark, are not "guaranteed" - you need to do static timing analysis with Vivado to get the real numbers.

Take a look at this post on constraining edge aligned source synchronous DDR interfaces to help you construct your constraints.

Since 212.5MHz is reasonable for the internals of the FPGA, you can consider using an IDDR instead of an ISERDES for the capture. This gives you the option of using either the BUFIO or the BUFR to clock the IDDR. In the past, my experiments have shown that you get slightly better margin using the BUFR alone.

So you should write the capture logic, write your constraints (don't forget clock jitter and duty cycle uncertainty) and do static timing analysis - you can even try with the BUFIO+BUFR or the BUFR alone to see which gives you the most margin (the largest sum of setup margin and hold margin). You should then adjust your tap settings on the IDELAYs (which you will likely need). You can put IDELAY on the data only, on the clock only, or on both - again, I have found that the best margin is when the IDELAY is on the data only (but my experiments are pretty old).

All this being said, a 1.97ns window should be wide enough. These kind of interfaces become questionably viable at around 1.5ns, but pretty solid at 1.75ns. With 1.95ns (even in a -1) you should be fine (but test it anyway!).

Avrum

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avrumw
Guide
Guide
171 Views
Registered: ‎01-23-2009

Good job!

Yes, you have analyzed this correctly. With a window of 1.97ns you should be able to do static capture of the interface using "ChipSync" clocking (using the BUFIO and BUFR - or just the BUFR only). And the Tpscs/Tphcs are the correct numbers to be looking at. A small word of warning, though, these numbers, while in the right ballpark, are not "guaranteed" - you need to do static timing analysis with Vivado to get the real numbers.

Take a look at this post on constraining edge aligned source synchronous DDR interfaces to help you construct your constraints.

Since 212.5MHz is reasonable for the internals of the FPGA, you can consider using an IDDR instead of an ISERDES for the capture. This gives you the option of using either the BUFIO or the BUFR to clock the IDDR. In the past, my experiments have shown that you get slightly better margin using the BUFR alone.

So you should write the capture logic, write your constraints (don't forget clock jitter and duty cycle uncertainty) and do static timing analysis - you can even try with the BUFIO+BUFR or the BUFR alone to see which gives you the most margin (the largest sum of setup margin and hold margin). You should then adjust your tap settings on the IDELAYs (which you will likely need). You can put IDELAY on the data only, on the clock only, or on both - again, I have found that the best margin is when the IDELAY is on the data only (but my experiments are pretty old).

All this being said, a 1.97ns window should be wide enough. These kind of interfaces become questionably viable at around 1.5ns, but pretty solid at 1.75ns. With 1.95ns (even in a -1) you should be fine (but test it anyway!).

Avrum

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Bareil761
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Registered: ‎06-04-2020

Hehe! Thanks.

I will do as you suggest and experiment a little with the options.

About the IDELAYS, what is the best way to adjust it? Oscilloscope on data and clock? If yes, I may add a small coax connector on the clock and a data line to help with debugging.

I remember having used IDELAYS in a dynamic fashion using a phase detector. Is that still possible with the Zynq architecture?

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avrumw
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Guide
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Registered: ‎01-23-2009

About the IDELAYS, what is the best way to adjust it?

Using static timing analysis.

Once you have all the I/O and clocking stuff designed and you have proper constraints you can look at the timing results. The tool will give you the worst setup margin and the worst hold margin (one or the other may be negative - as long as the sum of them is positive the interface is probably viable). Based on these margins you can determine how much additional delay needs to be added (and to which path - clock or data). Knowing that each IDELAY tap is approximately Trefclk/64, set the IDELAY to the proper number of taps and run static timing analysis again. If necessary fine tune the tap values after the second run.

With this process you can find the tap values that give you the best margins - you should aim for your setup margin and hold margin to be roughly equal - that gives you the most room for error in either direction.

I remember having used IDELAYS in a dynamic fashion using a phase detector. Is that still possible with the Zynq architecture?

It is definitely possible - this is called dynamic calibration or dynamic phase adjust, and can be done with the IDELAYs which have a dynamic mode where you can increase or decrease the number of taps one at a time using a simple INC/DEC interface. However, when possible, it is preferable to do the capture statically as described above - design an interface that passes static timing analysis with the best setup and hold margin.

Avrum