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Registered: ‎02-12-2018

are more restrictive constraints override less restrictive constraints?

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hello,

 

If  I have two conflicting constraints, which one takes precedence? The latest one, or the more restrictive one?

 

thank you

1 Solution

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avrumw
Guide
Guide
1,216 Views
Registered: ‎01-23-2009

The answer to this question is complicated...

 

Constraints of different types have different priorities. The following types of constraints are in descending order

  - set_clock_groups

  - set_false_path

  - set_max_delay

  - set_multicycle_path

  - (normal constraints - create_clock)

 

If two constraints are of the same type, then there are priorities based on how they are specified. These depend on if the path is specified between cells/pins (higher) or between clocks (lower), and the combination of -from/-through/-to (the more specific wins).

 

Constraint priority is documented in the "Using Constraints" User Guide (UG903) in the section on XDC Precedence (Chapter 7).

 

But, assuming they are the same type of constraint specified the same way, then the later one (NOT the more restrictive one) wins.

 

In project mode, though, things get even more complicated since the order in which different constraint files get read depend on a number of factors:

  - the order of the XDC file (normal, early, late)

  - whether the XDC is a user XDC or an IP's XDC

 

Avrum

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5 Replies
avrumw
Guide
Guide
1,217 Views
Registered: ‎01-23-2009

The answer to this question is complicated...

 

Constraints of different types have different priorities. The following types of constraints are in descending order

  - set_clock_groups

  - set_false_path

  - set_max_delay

  - set_multicycle_path

  - (normal constraints - create_clock)

 

If two constraints are of the same type, then there are priorities based on how they are specified. These depend on if the path is specified between cells/pins (higher) or between clocks (lower), and the combination of -from/-through/-to (the more specific wins).

 

Constraint priority is documented in the "Using Constraints" User Guide (UG903) in the section on XDC Precedence (Chapter 7).

 

But, assuming they are the same type of constraint specified the same way, then the later one (NOT the more restrictive one) wins.

 

In project mode, though, things get even more complicated since the order in which different constraint files get read depend on a number of factors:

  - the order of the XDC file (normal, early, late)

  - whether the XDC is a user XDC or an IP's XDC

 

Avrum

View solution in original post

viviany
Xilinx Employee
Xilinx Employee
1,051 Views
Registered: ‎05-14-2008

It depends.

For different constraints, for example, create_clock and set_false_path, it is the more restrictive one taking procedure.

For the same type of constraints, for example, two create_clock constraint, it is the latest one (the last loaded) if the two constraints get the same objects. If the objects are partial overlapping, the constraint that queries more specific objects takes procedure.

For example, the second constraint below takes procedure over the first one for the objects it queries.

set_false_path -from [get_clocks clk1] -to [get_clocks  clk2]

set_false_path -from [get_clocks clk1] -to [get_cells xxxxxxxx]

 

For more information, you can refer to Chapter 7 "XDC Precedence" in UG903.

-vivian

 

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0 Kudos
1,034 Views
Registered: ‎02-12-2018

thank you for the fast response.

 

I did not understand the following

    If a string instead of an object is passed to the constraint, the Tcl interpreter uses the
    following sequence to determine which object matches the string:
    1. port
    2. pin
    3. cell 
    4. net

(source: UG903)

 

I can address the type of object I want, specifically. For example:

 

get_ports -regexp {.*} 
get_cells -hierarchical -regexp {.*}

 

 

Another doubt, with false path of higher priority than multicycle, and cells of higher priority than clocks,

is it valid to have a set of cells as multicycle and their clocks as false path, such that false path is applied to all transitions between clk1 and clk2 except for the cells that have multicycle?

 

thank you

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hongh
Moderator
Moderator
1,031 Views
Registered: ‎11-04-2010
All false path constraints have higher priority than set_multicycle_path.
It is invalid to have a set of cells as multicycle and their clocks as false path! No paths will have multicycle constraint.
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viviany
Xilinx Employee
Xilinx Employee
1,020 Views
Registered: ‎05-14-2008

No. False path always has higher priority than multicycle path. They are different types of constraints, so the more restrictive one takes procedure.

 


@theultimatesource wrote:

thank you for the fast response.

 

I did not understand the following

    If a string instead of an object is passed to the constraint, the Tcl interpreter uses the
    following sequence to determine which object matches the string:
    1. port
    2. pin
    3. cell 
    4. net

(source: UG903)

 

This is referring to constraints like below, which uses strings for options instead of [get_*] commands.

 

set_false_path -from abc/def/ghi  -to  opq/rst/uvw

 

-vivian

 

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Don’t forget to reply, kudo, and accept as solution.
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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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